Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-07
2006-11-07
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07134102
ABSTRACT:
A system, an automatic machine-implemented method, and a machine-readable medium recording a set of instructions to perform such method are provided for de-compacting a layout for a portion of an integrated circuit. According to the method, a spacing is enlarged between neighboring features of a path of a plurality of paths of the layout provided that the length of the path does not then exceed a predetermined dimensional constraint and connectivity is maintained between the neighboring features and any features of the layout to which they are connected. This process is repeated to enlarge at least one other spacing of the layout.
REFERENCES:
patent: 6110222 (2000-08-01), Minami et al.
patent: 6301686 (2001-10-01), Kikuchi et al.
patent: 6385758 (2002-05-01), Kikuchi et al.
patent: 6526555 (2003-02-01), Teig et al.
patent: 6536012 (2003-03-01), Mizuno
patent: 6539533 (2003-03-01), Brown, III et al.
patent: 6576147 (2003-06-01), Mukai
patent: 6584599 (2003-06-01), Fujii
patent: 6651235 (2003-11-01), Dai et al.
patent: 6832364 (2004-12-01), Heng et al.
patent: 6874133 (2005-03-01), Gopalakrishnan et al.
patent: 6880134 (2005-04-01), Drennan
patent: 2004/0225986 (2004-11-01), Lin et al.
Allan, G., et al., “An Yield Improvement Technique for IC Layout Using Local Design Rules,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 11, 1992, pp. 1355-1362, vol. 11, No. 11.
Bamji, C., et al., “Enhanced Network Flow Algorithm for Yield Optimization,” Proc Des Autom Conf; Proceedings—Design Automation Conference, Jun. 3, 1996, pp. 746-751.
Maly, W., et al., “Design of Manufacturability in Submicron Domain,” Computer-Aided Design, IEEE/ACM International Conference on San Jose, CA, Nov. 10-14, 1996, pp. 690-697.
Chotin, E., et al., “A Design Planner Including a Fast Predictive Floorplanning Tool,” Euro ASIC '90, May 29, 1990, pp. 208-213, Paris, France.
Infineon - Technologies AG
Rossoshek Helen
Slater & Matsil L.L.P.
Thompson A. M.
LandOfFree
Automated layout transformation system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automated layout transformation system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated layout transformation system and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3670000