Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-05
2003-01-07
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S736000
Reexamination Certificate
active
06505324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing and more particularly to a process of blowing fuses within a semiconductor device.
2. Description of the Related Art
An application specific integrated circuit (ASIC) might contain some number of dense syncronous random access memory (SRAM) macros, an electronic chip identification (ECID) macro, and some number of embedded dynamic random access memory (eDRAM) macros, all of which contain laser fuses. The automated process for conversion of test data to fuseblow x-y locations needs to be flexible enough to handle various constraints imposed by the diverse nature of the ASIC business. ASIC designs are quite varied with respect to utilization of these types of macros.
The devices on the chip (e.g., SRAM, eDRAM, etc.) are tested, preferably using a built-in self test (BIST) design. Upon detection of a defect, select fuses are blown to permanently logically disconnect the defective devices from the circuit. Commonly these defective devices are replaced with redundant devices (again by selectively blowing fuses).
An example of a typical ASIC design is shown in FIG.
1
. The example in
FIG. 1
has five SRAM macros
100
-
104
, 2 eDRAM macros
105
,
106
and an ECID macro
108
. The SRAMs in this example are tested from two separate multiple-array-built-in-self-test (MABIST) controller macros, A (
110
) and B (
111
). Fuses for the SRAM macros reside in separate FUSE macros
112
-
116
, as shown. The BIST design
120
,
121
and FUSES
122
,
123
for eDRAM macros
105
,
106
are included within each eDRAM macro. The ECID macro
108
contains fuses
109
but is different, in that the values to be blown reflect non-test related data (chip identification data).
The SRAM macros
100
-
104
and eDRAM macros
105
,
106
are similar, in that test data is used to determine which fuses need to be blown. These macros differ in the complexity associated with correlating test measurements to desired fuse blow x-y locations. The SRAM macros
100
-
104
use external MABIST controllers
110
,
111
to measure the test data, and an external fuse macro
114
,
115
to which the test data must be correlated. The BIST logic
120
,
121
and fuses
122
,
123
for the eDRAMs
105
,
106
are self-contained. As a result, the SRAM macros
100
-
104
need to have net-tracing performed to assist the test to physical x-y correlation, whereas the eDRAM macros
105
,
106
do not.
The ECID (electronic chip identification) macro is used to encode Lot#, Wafer ID, Chip X-Y, etc. This data is created from software which uses this information as an input. This information is later used to identify a module and enable a correlation to the manufacturing process in-line data and wafer final test data.
The conventional laser fuse blow process includes steps which are manually performed for each different part number that requires laser fuse blow. The designer and/or product engineer will manually extract the information needed for laser fuse blow from the test manufacturing data (TMD
208
) and physical data or Very-Large-Scale-Integration (VLSI) In-core Model (VIM).
As the laser tool sweeps over the fuses, corresponding measured logical “1” latch data will direct the laser tool to pulse the laser beam, thereby blowing the desired fuse as dictated by the test data. The actual correspondence between measured latches and specific fuse x-y loactions must be specified in a correspondence list.
In the TMD, certain latches are specified to be measured during test. Some of these latches contain stored failing address locations and redundancy enable bits which specify that certain redundant rows or columns within a certain array on the chip must be selected. These latches must be identified manually by reading the TMD and listing them in the correspondence list according to the name specified for them within the TMD. These measured values will correspond to actual fuses within the chip that must be blown using a laser beam. Which fuses are blown will depend upon which of the above specified latches are measured at a logical value of “1”.
Also, the physical locations of the fuses with respect to the chip (
0
,
0
) coordinate must be provided to the laser tool, so that it knows where to point the laser beam. In the VIM, macros containing fuses are identified by manually reading the VIM to find them. As previously mentioned, there are various types of macros containing fuses. If the macro is a fuse macro for SRAMs, then further tracing of the nets within the VIM is necessary in order to find the fuse macro's corresponding MABIST controller. Once this is known, then the latch name within the MABIST controller can be found in the correspondence list, which was generated when reading the TMD. The correspondence of fuses within the fuse macro and latches within the corresponding MABIST controller can then be specified in the correspondence list. The x-y coordinates of the fuses within the fuse macro are manually transposed to chip level coordinates, and these chip level coordinates are manually entered in the correspondence list next to the fuse's corresponding latch. A similar operation is performed for eDRAM macros, although the extra tracing within the VIM isn't necessary, since the BIST latches and the fuses exist within the same macro, and the correspondence is fixed within the macro. The fuse x-y coordinates for the eDRAM fuses must also be manually transposed to chip x-y coordinates and manually added to the correspondence list. For the ECID macro, the fuse x-y coordinates are manually listed in a specified order in the correspondence list next to a manually specified indentifier. There are no latches measured in the TMD for ECID. The manual steps involved in creating the correspondence list are laborious and time consuming. Errors are easily made and very difficult to debug when the laser fuse blow fails.
The product engineer for the specified part number will manually read the TMD and the VIM to create the correspondence list. This list is then provided to the fuse software engineer, who manually codes a fuse blow table (FBT) specific to that part number. The manual steps involved in creating the FBT are very prone to error. Once this FBT is debugged, the fuse mapping software will automatically convert tester data for each chip to fuseblow data. However, this FBT must be manually created and debugged for each different part number.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip including creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data.
The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file. Creation of the fuse map file includes categorizing the fuse macros, flattening hierarchy in the design, and progressively matching the fuse macros in the design to the physical pin locations using a fuse location file.
Each fuse macro has a unique fuse location file and creation of the fuse map file also includes converting the fuse location information in each fuse location file such that the fuse location information is relative to the semiconductor chip as a whole by noting individual fuse macro locations, mirroring, and orientation. Blowing of selected fuses includes matching the fuse map file to a wafer map. The fuse location file includes keywords that identify an associated fuse macro, a type of fuse
Cowan Bruce
Distler Frank O.
Ollive Mark F.
Ouellette Michael R.
Panner Jeannie H.
Kotulak, Esq. Richard M.
McGinn & Gibb PLLC
Whitmore Stacey
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