Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-03
2004-12-21
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000
Reexamination Certificate
active
06834380
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to layout and floor planning of electronic devices and systems.
2. Background Information
Tools for automated component placement have become commonplace in the design and fabrication of modern electronic systems and devices (such as integrated circuits).
FIG. 70
shows a flowchart for such a tool, which translates a logical or schematic circuit description into a template for the placement of components within an actual prototype. Input data for an automated placement tool may include a functional description of logical flow or signal flow, e.g. as embodied in a SPICE (for ‘Simulation Program (with) Integrated Circuit Emphasis’) netlist or a hardware description language (or ‘HDL’) file. The tool may also receive data such as constraints on the size and/or shape of the finished prototype. When used to design integrated circuits, automated placement tools are also called ‘floorplanners,’ although similar tools may also be used to design multichip modules (MCMs), circuit boards or subassemblies, or even complete assemblies such as end-user and consumer products.
It is known that if the template complies with certain rules of layout design, the likelihood of unforeseen complications in the operation of the resulting prototype will be reduced. One such layout design rule is to minimize the length and complexity of interconnections by placing highly connected components close to one other. Also, such rules dictate against the use of long parallel signal traces in the placement template in order to minimize crosstalk, coupling, and loading effects in the fabricated circuit, thus helping to ensuring signal integrity system-wide.
Even when the final placement template complies with predetermined layout design rules, however, the resulting prototype will often fail to function as expected. One reason for such failure is that the layout design rules do not account for the actual electromagnetic interactions between the different elements of the system. Electromagnetic interference and electromagnetic compatibility are strongly dependent on the physical placements of the various circuit elements and the interconnections between these elements and the assignment of power and ground terminals. Also, the effects of electromagnetic emissions within the circuit become more pronounced as component sizes are reduced and component population densities and operating frequencies are increased. As a result, first-pass design of highly integrated components, especially those intended for operation at microwave frequencies, has become virtually impossible.
Such problems may arise even if a part of the design has been used successfully in an earlier prototype. For example, it is becoming increasingly common to use circuit blocks in more than one design. Such a block may have been designed from scratch for an earlier application, for example, or it may have been purchased as a piece of intellectual property (IP) (also called an ‘IP core’) from an outside vendor. A layout tool that verifies compliance with layout design rules may fail to predict problems that arise when such a block is used in a different environment: adjacent to different functional blocks, for example, or operating at a different frequency, duty cycle, or clock edge, or fabricated in a different process.
Moreover, the causes of such problems are not easily identified in the finished prototype. One reason is the difficulty of pinpointing the source of a troublesome emission from among a number of radiators. Therefore, corrective actions may be performed more or less blindly, while the precise causes for a problem remain unknown through several cycles of prototype revision, leading to inefficiencies of time and money. Not only does the design process become characterized by a costly iterative trial-and-error cycle, but certain corrective attempts (such as adding shielding) may even prove detrimental by adding weight, consuming volume, or even exacerbating the actual mechanism of interference.
For such reasons, it is desirable to enable a preventative approach to circuit layout by assessing electromagnetic interactions between circuit elements during the design phase, thus allowing potential problems to be identified and solutions to be evaluated quickly and easily before the costly process of realization has begun.
For portable products such as devices for wireless communications, there is demand for miniaturization, reduced weight and power consumption, and operation in unpredictable environments. These design requirements are in direct contradiction to enhanced performance requirements such as increased system functionality, communications bandwidth, and data throughput. The production of products that meet these sets of contradictory requirements cannot be accomplished without paying careful attention to component/device electromagnetic compatibility early in the design phase. Therefore, it is desirable to have tools to support electromagnetic compatibility-driven design of electronic devices and systems.
SUMMARY
An apparatus according to an embodiment of the invention comprises an electromagnetic field calculator and an electromagnetic interference calculator coupled to the electromagnetic field calculator. The electromagnetic field calculator receives (A) information relating to a relative placement of a plurality of components and (B) a plurality of emissions profiles, each emissions profile relating to one among the plurality of components and outputs information regarding an induced electromagnetic field. The electromagnetic interference calculator receives (C) a plurality of susceptibility profiles, each susceptibility profile relating to one among the plurality of components, and (D) the information regarding an induced electromagnetic field and outputs information regarding effects caused by the induced electromagnetic field.
REFERENCES:
Kashyap, “An expert system for predicting radiated EMI form PCB's”. IEEE, 1997, pp. 444-449.*
Marano, “Field tests on telecommunication systems: an eavaluation of the radiated emissions by near filed probe”. IEEE, 1998, pp. 918-923.*
Childs, “Fast interactive EMC analysis for design engineers”. IEEE, 1995, pp. 1-7.*
Natesan, “Performance driven placement for cell-based design”. IEEE, 1995, pp. 237-240.
Brelon Charles O.
Pappas George C.
Qualcomm Incorporated
Wadsworth Philip R.
Whitmore Stacy A.
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