Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-30
2010-02-02
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07657858
ABSTRACT:
A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.
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Chen Youang Pin
Patel Nirav
Reddy Raghunatha Reddy Lakki
Srujana Sireesha Tulluri Lakshmi Naga Venkata
Subramanian Sivaramakrishnan
Agere Systems Inc.
Chiang Jack
Lin Aric
Ryan & Mason & Lewis, LLP
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