Automated DMA engine for ATA control

Details Automated DMA engine for ATA control Automated DMA engine for ATA control

2000-05-22

2004-02-24

Perveen, Rehana (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S024000, C710S036000, C710S039000, C710S043000, C710S048000

Reexamination Certificate

active

06697885

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to ATA-to-peripheral device bi-directional data transfer systems, and more particularly, to an advanced ATA adapter implementing a command chaining technique to de-couple the host command sequence from channel execution.
BACKGROUND OF THE INVENTION
The performance of ATA devices has increased dramatically over the last few years, particularly following introduction of the overlapped and queued command set. However, systems using these faster devices have not exhibited all of the expected benefits. This limited performance improvement can be traced to the design and implementation of the ATA host adapters currently in use, with the problem being amplified by the design of the Standard ATA driver software used in Windows® operating systems. These drivers effectively treat ATA transfers as a single-threaded entity, with correspondingly long latencies, required to have a host system fully service interrupt requests.
There are a number of factors that contribute to the time taken by a host computer to service a I/O request. In most operating systems, register access requires a subroutine call involving considerable processor overhead. The register access sequence of actions requires seven separate PCI 8-bit I/O transfers. Each register access takes a minimum of 4 PCI clocks (120 ms at 33 MHz) plus the ATA cycle time for each transfer. In many cases, the ATA devices are set to mode 0 for command-block transfers. In mode 0, the ATA cycle time is 600 ms for each access. This time is in addition to the 120 ns required for a PCI transfer, making a total of 720 ns per register access or 5040 ns (5 us) for a complete command set up sequence. During this period, the PCI bus and the processor are unavailable for further functions.
The data transfer period depends on the ATA protocol in use, the size of the ATA adapter FIFO, the size of the host cache line, and the overall PCI bus utilization. During bus master transfers, the memory and PCI usage is interleaved with the processor's requirements. Thus, the processor is able to fetch instructions and process them within its own pipeline, concurrent with the bus-master transfer. The normal unit of transfer requested by a Microsoft O/S is 4k Bytes. For an Ultra 100 system operating on a PCI-33 bus, the minimum transfer time would be 30 us, making the command set up time a minimum of 16% of the transfer time. When the transfer is complete, the ATA device may assert an interrupt. The host shall then read the ATA status register to determine if the transfer was successful and to clear any pending interrupt. Thus, for any one transfer, there is the potential for a long period of PCI bus utilization for command transfer and the need to service an interrupt.


REFERENCES:
patent: 5129064 (1992-07-01), Fogg et al.
patent: 5404550 (1995-04-01), Horst
patent: 5561816 (1996-10-01), Mitsuhira et al.
patent: 5721828 (1998-02-01), Frisch
patent: 5860083 (1999-01-01), Sukegawa
patent: 5903281 (1999-05-01), Chen et al.
patent: 6161154 (2000-12-01), Schultz et al.

Affiliated with

Also associated with

Rating

Automated DMA engine for ATA control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automated DMA engine for ATA control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated DMA engine for ATA control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3306018