Automated digital circuit design tool that reduces or...

Details Automated digital circuit design tool that reduces or... Automated digital circuit design tool that reduces or...

2011-03-29

2011-03-29

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S118000, C716S126000, C716S136000

Reexamination Certificate

active

07917882

ABSTRACT:
The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention generates a clocking system that includes a clock signal generator, control logic, enable logic, and at least one clock gater. The clock signal generator generates a clock signal that is distributed to various logic blocks of the digital circuit using a buffered clock tree. The enable logic receives input values from the control logic and provides a control signal to the clock gater. When enabled, the clock gater allows a clock signal to pass through to multiple registers. An early clock signal is provided to register(s) in the control logic, which allows for an increased clock frequency while still meeting timing constraints.

REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 6216255 (2001-04-01), Ito et al.
patent: 6301553 (2001-10-01), Burgun et al.
patent: 6473890 (2002-10-01), Yasui et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6809570 (2004-10-01), Francom
patent: 6883156 (2005-04-01), Khainson et al.
patent: 7003746 (2006-02-01), Hyduke et al.
patent: 7082579 (2006-07-01), Asai
patent: 7116150 (2006-10-01), Francom
patent: 7444277 (2008-10-01), Rich et al.
patent: 7480606 (2009-01-01), Tseng et al.
patent: 7653884 (2010-01-01), Furnish et al.
patent: 7673201 (2010-03-01), Chan et al.
patent: 7805697 (2010-09-01), Wood
patent: 2002/0188911 (2002-12-01), Asai
patent: 2003/0182634 (2003-09-01), Chang et al.
patent: 2004/0064793 (2004-04-01), Alpert et al.
patent: 2004/0107408 (2004-06-01), Sano et al.
patent: 2004/0168140 (2004-08-01), Chang
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2006/0150135 (2006-07-01), Hamada et al.
patent: 2008/0024173 (2008-01-01), Nagai et al.
patent: 2008/0028343 (2008-01-01), Sato et al.
patent: 2008/0216040 (2008-09-01), Furnish et al.
patent: 2010/0115477 (2010-05-01), Albrecht et al.
patent: 851581 (1998-07-01), None
patent: 10200380 (1998-07-01), None
patent: 2002366254 (2002-12-01), None

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