Automated design rule violation correction when adding dummy...

Details Automated design rule violation correction when adding dummy... Automated design rule violation correction when adding dummy...

2002-07-23

2004-04-06

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06718527

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to electronic circuits and more particularly to complex computer aided design layout and design rule verification of a design layout of, for example, an integrated circuit (IC) device or printed wiring board, in preparation for fabrication.
2. Description of the Related Art
Design of an electronic circuit, for example, an integrated circuit (IC), is a complicated and time consuming process.
FIG. 1
illustrates a typical design flow
100
of an integrated circuit device from conception through the generation of a fabrication ready design layout. Generally, design flow
100
commences with defining the design specifications or requirements, such as required functionality and timing, step
102
. The requirements of the design are implemented, for example, as a net-list or electronic circuit description, step
104
. The implementation can be performed by, for example, schematic capture (drawing the design with a computer aided design tool) or more typically, utilizing a high level description language such as VHDL, Verilog and the like. The implemented design is simulated to verify design accuracy, step
106
. Design implementation and simulation are iterative processes. For example, errors found by simulation are corrected by design implementation and re-simulated.
Once the design is verified for accuracy with simulation, a design layout of the design is created, step
108
. The design layout describes the detailed design geometries and the relative positioning of each design layer to be used in actual fabrication. The design layout is very tightly linked to overall circuit performance (area, speed and power dissipation) because the physical structure defined by the design layout determines, for example, the transconductances of the transistors, the parasitic capacitances and resistances, and the silicon area which is used to realize a certain function. The detailed design layout requires a very intensive and time-consuming design effort and is typically performed utilizing specialized computer aided design (CAD) or Electronic Design Automation (EDA) tools.
The design layout is checked against a set of design rules in a design rule check (DRC), step
110
. The created design layout must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule can be, for example, a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries can be specified for different sizes of geometries. DRC is a time-consuming iterative process that often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a DRC clean (violation free) design.
Circuit extraction is performed after the design layout is completed and error free, step
112
. The extracted circuit identifies individual transistors and interconnections, for example, on various layers, as well as the parasitic resistances and capacitances present between the layers. A layout versus schematic check (LVS) is performed, step
114
, where the extracted net-list is compared to the design implementation created in step
104
. LVS ensures that the design layout is a correct realization of the intended circuit topology. Any errors such as unintended connections between transistors, or missing connections/devices, etc. must be corrected in the design layout before proceeding to post-layout simulation, step
116
. The post-layout simulation is performed using the extracted net-list which provides a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that can occur due to signal delay mismatches. Once post-layout simulation is complete and all errors found by DRC are corrected, the design is ready for fabrication and is sent to a fabrication facility.
As electronic circuit densities increase and technology advances, for example, in deep sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and manufacturability and reliability of the circuit. For example, the density can be increased, redundant vias added, and the like. Creation of a design layout and performing DRC become critical time consuming processes. Performing a DRC and manipulation of the design layout often requires manual interaction from the designer. A reliable, automated technique for improving the design layout is needed.
SUMMARY
Accordingly, it has been discovered that automated techniques to correct certain rule violations with respect to non-design geometries can be used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit.
Accordingly, in one embodiment, adding non-design geometries to a design layout is accomplished by adding one or more non-design geometries to the design layout, the design layout including one or more design geometries; and correcting one or more design rule violations by removing a portion of the one or more non-design geometries; wherein correcting the one or more design rule violations includes: deriving non-design wide class objects from the one or more non-design geometries and design wide class objects from the one or more design geometries; wherein at least one of the non-design wide class objects and the design wide class objects have a virtual edge; and using the virtual edge in determining the portion of the one or more non-design geometries to be removed.
In another embodiment, the one or more design rule violations include a minimum spacing rule violation.
In another embodiment, any slivers of remaining non-design geometries are removed by performing a sizing down operation utilizing a sizing factor on the remaining non-design geometries, and performing a sizing up operation utilizing the sizing factor on a result of the performing the sizing down operation; wherein any of the remaining non-design geometries with a size smaller than a minimum size are removed.
In another embodiment, the sizing factor is slightly less than one half of a minimum width amount and the minimum size is the minimum width amount.
In another embodiment, at least one of the one or more non-design geometries is tied to power.
In another embodiment, at least one of the one or more non-design geometries is tied to ground.
In another embodiment, at least one of the one or more non-design geometries is merged with at least one of the one or more design geometries.
In another embodiment, removing the portion of the one or more non-design geometries causes at least one of the one or more non-design geometries to split into two or more smaller non-design geometries.
In another embodiment, re-deriving the non-design wide class objects from the one or more non-design geometries is performed after the portion of the one or more non-design geometries is removed.
In another embodiment, the portion of the one or more non-design geometries is determined for each of the non-design wide class objects and associated wide class design rules.
In another embodiment, the portion of the one or more non-design geometries is determined for each of the design wide class objects and associated wide class design rule.
In another embodiment, the portion of the one or more non-design geometries is generated by stretching and sizing erroneous edges of the design wide class objects.
In another embodiment, the portion of the one or more non-design geometries is generated by stretching and sizing erroneous edges of the non-design wide cla

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