Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-20
2002-12-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06490716
ABSTRACT:
TECHNICAL FIELD
The invention relates to the automated design of a programmable processor, and in particular, relates to the design of a processor instruction unit.
BACKGROUND
Over the last decade, the use of programmable processors has become pervasive, not only in conventional computing machines such as workstations and PCs, but also in a variety of other products such as telephones, games, vehicles, televisions, etc. While workstations and personal computer markets are converging on a small number of processor designs, the embedded systems market is enjoying an explosion of architectural diversity. This diversity is driven by widely varying demands on processor performance and power consumption, and is propelled by the possibility of optimizing architectures for particular application domains. Because of these varying demands and the advantages of optimizing a design for a particular application, it is often necessary to design an application specific processor rather than use an existing processor design. In view of the complexity of the design task and the pressure to reduce the time to market, there is a need for automation tools that assist the designer in creating the processor design.
The processor design generally includes a specification of the instruction format, a data path, and a control path. The instruction format specifies the instructions that the processor executes along with the specific bit encodings for each of the instructions. The data path specifies the functional units that execute the instructions, the register files that store the inputs and outputs of the instructions, and the interconnect that transfers data back and forth between the register files and functional units. Finally, the control path specifies how instructions are fetched from memory, decoded, and dispatched to the control ports in the data path, including the register file address ports and opcode input ports of the functional units.
An instruction unit is a general term for the control path component in the processor that fetches instructions from memory and decodes them. The design of the instruction unit is typically quite complex, particularly for Very Long Word Instruction (VLIW) processors. VLIW processors exploit instruction-level parallelism by issuing several operations per instruction to multiple functional units. Usually, the instructions are very wide and of variable width in order to minimize code size. The encoding of multiple operations into variable length instructions complicates the design of the instruction unit.
To date, the architects of programmable processor chips have had to design the instruction unit of the processor manually. While there are a number of software tools for digital logic synthesis, none of these tools are known to automate the design of the processor instruction unit. Therefore, there is a need for design tools that automate the design of instruction units, and their components.
SUMMARY
The invention relates to an automated method for designing a processor's control path. The method employs program routines implemented in software or hardware to automate the design of the control path based on the processor's instruction format and data path specification. It extracts parameters from a machine-readable description of the processor's instruction format specification, and generates a specification of the components in the control path.
The method involves a number of unique process steps for automating the design of a processor's control path. These process steps may be used individually, or in a variety of combinations, to automate the design of components in the processor's control path. In one design scenario, for example, the method generates a hardware description of the processor's control path from a specification of the processor's instruction format and a macrocell library of hardware components used to build the components in the control path. In this scenario, the processor's control path includes: 1) the data path (the IUdatapath) of an instruction from the processor's instruction cache to an instruction register that interfaces with the instruction decode logic, 2) the control logic for controlling the IUdatapath, and 3) the instruction decode logic. The method programmatically extracts instruction width requirements from the instruction format and uses this information to create macrocell instances for the hardware components in the IUdatapath. It also programmatically generates the decode logic (e.g., in the form of logic tables) from the instruction format specification. Finally, it programmatically generates the control logic for the IUdatapath. This control logic includes the logic that interconnects the instruction sequencer in the processor with the IUdatapath and controls an alignment network for aligning instructions in the processor's instruction register.
Each one of the process steps outlined above can be used individually to automate portions of the control path design. For example, one aspect of the method may be used to generate a hardware description of prefetch buffers in the control path based on the instruction format. Another aspect of the method may be used to generate the control logic that controls the prefetch buffers and interconnects the instruction sequencer in the processor with the IUdatapath. Yet another aspect of the method may be used to generate the alignment network. Finally, another aspect of the method may be used to generate the control logic that decodes the instructions and distributes the control signals to the processor's data path components.
Further advantages and features of the invention will become apparent with reference to the following detailed description and accompanying drawings.
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Gupta Shail Aditya
Rau B. Ramakrishna
Hewlett--Packard Company
Levin Naum
Smith Matthew
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