Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-03-31
2000-02-01
Ngoo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257207, 257208, 257532, H01L 2710, H01L 2900
Patent
active
060206160
ABSTRACT:
Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilcon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.
REFERENCES:
patent: 4453090 (1984-06-01), Sempel
patent: 4783692 (1988-11-01), Uratani
patent: 4786828 (1988-11-01), Hoffman
patent: 4812962 (1989-03-01), Witt
patent: 5266821 (1993-11-01), Chern et al.
patent: 5408538 (1995-04-01), Kitakado et al.
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5475766 (1995-12-01), Tsuchiya et al.
patent: 5546225 (1996-08-01), Shiraishi
patent: 5553273 (1996-09-01), Liebmann
patent: 5576565 (1996-11-01), Yamaguchi et al.
patent: 5606197 (1997-02-01), Johansson et al.
patent: 5616940 (1997-04-01), Kato et al.
patent: 5631492 (1997-05-01), Ramus et al.
patent: 5761075 (1998-06-01), Oi et al.
patent: 5795683 (1998-08-01), Uno et al.
patent: 5796148 (1998-08-01), Gorman
patent: 5798937 (1998-08-01), Bracha et al.
patent: 5844301 (1998-12-01), Van Roosmalen
patent: 5872862 (1999-02-01), Okubo et al.
Bothra Subhas
Findley Paul R.
Ngoo Ngan V.
VLSI Technology Inc.
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