Automated design of on-chip capacitive structures for...

Details Automated design of on-chip capacitive structures for... Automated design of on-chip capacitive structures for...

1999-11-30

2001-12-04

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06327695

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to an automated method for designing on-chip capacitive structures to suppress inductive noise in high performance integrated circuit applications.
2. Description of the Related Art
The continuing trend in modern integrated circuit design is to decrease the physical size of a chip, increase circuit layout density, and increase operating speeds. Although designers have been able to design very high frequency devices that operate at lower power supply voltages, a substantial increase in inductive noise due to a chip's package and printed circuit board (PCB) routing has also occurred. In the past, off-chip discrete capacitor components have been attached directly onto a chip's package or the PCB in order to capacitively shunt the ever increasing inductive noise. Although this was worked with some success in the past, as devices continue to be improved to operate at faster speeds and lower power supply voltages, the allowable noise margin for the inductive noise has also continued to decrease. That is, as devices become faster and faster, a device may fail to operate properly if the inductive noise rises above predetermined allowable noise margins, which necessarily decrease as speeds increase.
FIG. 1A
is a simplified diagram of a PCB
100
having a packaged chip integrated onto the PCB
100
. In this example, a chip
102
is integrated onto a package
104
, which has a plurality of traces
106
that connect the chip
102
to the lead pins of the package
104
. As mentioned above, a customary method of suppressing the inductive noise is to attach off-chip discrete capacitor components
108
or
112
on the package
104
or the PCB
100
, respectively. Although this has worked in the past, the increased amount of inductive noise produced in devices having clock frequencies above about 200 MHz has been found to be too much for off-chip discrete components to handle. As a result, many high speed devices suffer in having noise margins that exceed the amount recommended for proper high performance operation.
For illustration purposes,
FIG. 1B
shows a graph
150
that plots allowable noise margins vs. clock frequencies. A plot line
152
illustrates that as clock frequencies increase, the allowable noise margins also decrease. For example, a point A shows that for a 0.5 micron technology device, the allowable noise margin is slightly below about 12% of the voltage source (i.e., Vdd) used.
FIG. 1C
provides a graph
160
that plots the allowable noise margins as a percentage of the voltage source, where a full rail Vdd is 100%.
Referring back to
FIG. 1B
, a point B illustrates that the allowable noise margin drops to about 10% of the voltage source used for a 0.35 micron technology device. A point C illustrates that the allowable noise margin drops again to about 8% of the voltage source used for a 0.25 micron technology device, and a point D illustrates that the allowable noise margin drops to about 6% of the voltage source used for a 0.18 micron technology device.
FIG. 1C
also plots the allowable percentage noise margin for a 0.25 micron technology device.
As can be appreciated, the faster the device gets, the smaller the allowable noise margin becomes, and because lower voltage sources are used for smaller technology devices, the actual voltage magnitude of the allowable noise margin also decreases more substantially. To illustrate this point, reference is drawn to
FIG. 1D
, where the exemplary micron technologies are compared with respect to the allowable noise margins (NMs), and the resulting voltage magnitudes.
For example, for a 0.5 micron technology device, the voltage source is 5V and the allowable noise margin is about 12%. This therefore produces a noise margin voltage magnitude of about 0.6V. This can then be compared to a 0.18 micron technology device which has a voltage source of 1.8V, and an allowable noise margin of about 6%. The resulting noise margin voltage magnitude will be about 0.1V. Thus, not only does the allowable noise margin decrease as device speed increases, but the voltage supply used in smaller micron technology devices also decreases.
Consequently, that faster and smaller the device, the less it will be able to handle even very small noise margins. Further yet, the faster the device becomes, even more inductive noise tends to be produced. To remedy this, some designers have begun to custom design on-chip capacitors into existing designs. Unfortunately, the design of custom on-chip capacitors has the disadvantage of requiring a substantial amount of chip area, which in some cases may be up to 10% or more additional chip area. Further yet, the design of custom on-chip capacitors also requires time consuming manual examination and modification of the photolithography masks used to design the multi-layered devices.
As can be appreciated, this type of custom design can be very costly, however, this expense has become necessary in order to appropriately suppress the growing levels of inductive noise produced in higher performing devices.
In view of the foregoing, there is a need for automated techniques that enable fast and efficient design and fabrication of on-chip capacitive structures for suppressing power supply inductive noise.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an automated technique for designing on-chip capacitive structures over dummy active regions, that are intelligently dispersed throughout an integrated circuit chip to reduce topographical variations. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a network of on-chip capacitive structures for suppressing power supply inductive noise is disclosed. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.
In another embodiment, a method for making a network of on-chip capacitive structures for suppressing power supply inductive noise is disclosed. The method includes designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. Designing a network of dummy polysilicon lines that are configured to overlie selected dummy active regions, and the network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions define capacitor structure locations for the network of on-chip capacitive structures.
In yet another embodiment, a system for designing a network of on-chip capacitive structures for suppressing power supply inductive noise is disclosed. The system includes means for designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The plurality of dummy active regions are fattier

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