Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-08
2005-03-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06865724
ABSTRACT:
A computer implemented method and system of identifying crosstalk in a circuit provides significant benefits over conventional manual approaches. The method provides for selecting a plurality of signals from computer aided design (CAD) data based on a set of electromagnetic interference (EMI) criteria. Trace-to-trace run length values of traces corresponding to the signals are measured in accordance with a trace spacing. The method further provides for indication which traces have one length values above a predetermined threshold.
REFERENCES:
patent: 5781446 (1998-07-01), Wu
patent: 6185722 (2001-02-01), Darden et al.
patent: 403003347 (1991-01-01), None
Lai et al., “Quadratic Programming Mehtod for Interconnection Crosstalk Minimzation”, IEEE, 1999.
Cecil Damon M.
Eisenberg Alan S.
Vadim Sherman
Xue Zhen
Bowers Brandon
Garbowski Leigh M.
Intel Corporation
Jordan B. Delano
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