Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-31
2003-06-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06581196
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Technical Field
The present invention generally relates to the identification of crosstalk in electrical circuits. More particularly, the invention relates to a system and method of identifying crosstalk that involves automatically determining trace-to-trace run length values for the circuit.
2 Discussion
In the semiconductor industry increased functionality, faster performance and lower operating voltages have placed a new set of demands on the packages serving as an interface between integrated.circuits (ICs) and printed wiring boards (PWBs). For example, higher signaling rates have been shown to increase unwanted electromagnetic emissions in ICs, PWBs and semiconductor packages. Furthermore, regulatory organizations such as the Federal Communications Commission (FCC) have restricted electromagnetic interference (EMI) emissions to levels that have forced semiconductor suppliers, systems companies and manufacturing foundries to address the issue of EMI in order to maintain viability in such a competitive industry.
“Crosstalk” occurs when current paths through a structure such as a PWB or semiconductor package carry signals that interfere with one another. Thus, crosstalk can occur between signal pins.in a connector, between vias in a substrate, between traces in a PWB, and in numerous other scenarios.
While a number of approaches have been used to identify crosstalk between traces in a PWB, there remains room for significant improvement. For example, one approach is to test a fully designed and manufactured product under operating conditions for EMI emissions. While this approach is perhaps the most direct, it will be appreciated that in the event that the measured EMI emissions are above the permitted levels, redesign of the trace layout may necessary. It will further be appreciated that such a result may be quite costly and therefore has significant practical limitations.
Another approach is to produce a hard copy of the trace design, and to manually measure trace-to-trace run length values. This approach relies on the widely accepted understanding that when traces run along side each other at a given spacing for greater than a predetermined distance, the likelihood for EMI emissions increases (particularly in the case of high frequency signals such as clock signals). The difficulty with the manual approach, however, is that it is relatively labor intensive and can therefore be cost prohibitive.
Yet another approach is to use a commercially available computer aided design (CAD) tool to manipulate the traces of the circuit in order to determine trace-to-trace run length values. Under this approach, a first trace is selected using a graphical interface, and the segments of the selected trace are copied to a distance equal to the predetermined trace spacing in order to simulate the region that other traces should avoid in order to minimize crosstalk. Thus, the user may determine run length values by selecting trace segments falling in the simulated region with the CAD tool. This approach requires a significant amount of user manipulation, skill and time in order to select the desired segments and traces, and to calculate the desired values.
REFERENCES:
patent: 6028989 (2000-02-01), Dansky et al.
patent: 6110222 (2000-08-01), Minami et al.
patent: 6374391 (2002-04-01), Yamada
Cecil Damon M.
Eisenberg Alan S.
Vadim Sherman
Xue Zhen
Bowers Brandon
Siek Vuthe
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