Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-27
2008-05-27
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11261960
ABSTRACT:
Automated techniques may correct certain rule violations, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. Violations of enclosure design rules, those specifying the minimum amount that a geometry on a first layer must overlap a geometry on a second layer of a design layout, and more specifically, violations of asymmetric enclosure design rules, may be corrected using a geometric construction algorithm. This geometric construction algorithm may use the known width of the geometry on the second layer and a predetermined size factor to determine other parameters for constructing and placing a patch over a violation, such as the patch width, the patch length, the patch starting edge, and the patch direction. Patches may be constructed using different predetermined size factors when asymmetric enclosure violations are located on first layer geometries in different width ranges.
REFERENCES:
patent: 6536023 (2003-03-01), Mohan et al.
patent: 6883149 (2005-04-01), Li et al.
patent: 6892368 (2005-05-01), Li et al.
patent: 2006/0253817 (2006-11-01), Meyer et al.
Dinh Paul
Kowert Robert C.
Mayertons, Hood, Kivlin, Kowert & Goetzel, P.C.
Sun Microsystems Inc.
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