Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2000-06-05
2002-07-09
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C029S025010
Reexamination Certificate
active
06417076
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor wafer fabrication, and more particularly to the protection of global alignment mark sites during etching and other fabrication processes.
BACKGROUND
Rapid thermal process (RTP) reactors have been utilized for some time in the processing of semiconductor wafers. RTP reactors have a significantly shorter process cycle than conventional reactors. For example, while conventional reactors require forty to ninety minutes for processing wafers, RTP reactors need only two to fifteen minutes.
One attendant problem created through the use of RTP reactors is that a high temperature gradient often is generated across the wafer-in-process which leads to plastic deformation. The deformation that occurs is more highly non-correctable along the periphery of the wafer-in-process where non-patterned areas exist.
Global alignment marks are generally sited in non-patterned areas at or near a wafer's periphery, thus rendering them more susceptible to deformation effects than other non-patterned areas nearer the center of the wafer. A suggested method for reducing the deformation effects in global alignment mark (also known as combi) sites is to pattern the sites to reduce the amount of non-patterned area. U.S. patent application Ser. No. 09/587,297, entitled OVERLAY ERROR REDUCTION BY MINIMIZATION OF UNPATTERNED WAFER AREA, having as a named inventor Ziad R. Hatab, filed on Jun. 5, 2000, describes partial patterning combi sites to diminish non-correctable misalignments. The entire disclosure of the Hatab application is incorporated herein by reference.
Although this technique of partial patterning combi sites diminishes non-correctable misalignments, one difficulty encountered is that partial patterning using a stepper is time consuming and more difficult to accomplish than full-field patterning.
There exists a need for a less time intensive procedure for patterning combi sites while simultaneously protecting the combi sites from damage due to one or more subsequent processing steps.
SUMMARY
The invention provides a semiconductor wafer-in-process which includes a substrate, one or more global alignment sites located on a surface of the substrate, each site including a global alignment mark, a partially developed layer of photoresist material over the global alignment mark, and a globule of protective material deposited over one or more of the global alignment sites which protects the global alignment sites during an etch of a wafer using the patterned photoresist material.
The invention also provides a semiconductor wafer-in-process that includes a substrate, one or more global alignment sites located on a surface of the substrate, each site including a global alignment mark, conductive patterning positioned peripheral to the marks, and a globule of protective material deposited over one or more of the global alignment sites and a portion of the conductive patterning to protect the sites and the conductive patterning during subsequent etching operations.
The invention further provides a system for depositing protective material globules on a wafer-in-process. The system includes a protective material deposition device including a chamber adapted to receive and retain protective material and a nozzle extending from said chamber. The system also includes a base upon which the wafer-in-process is supported.
The invention further provides a method of fabricating a semiconductor wafer having one or more global alignment sites. The method includes coating the wafer with a photoresist material including over the global alignment sites, exposing one or more portions of the photoresist material including over the global alignment sites, developing the exposed portions of the photoresist material, and depositing a protective material globule over one or more global alignment sites to protect them during an etch of the wafer.
The invention also provides a method of protecting conductive patterning during fabrication of a semiconductor wafer-in-process having a substrate, one or more global alignment sites, each having a global alignment mark. The method includes fabricating conductive patterning at a position peripheral to the global alignment mark, patterning a photoresist material layer on the wafer, and depositing a protective material globule over the alignment marks and at least partially over the conductive patterning to protect both during an etch of the wafer using the patterned photoresist material.
These and other advantages and features of the invention will be more readily understood from the following detailed description which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 4779004 (1988-10-01), Tew et al.
patent: 5710407 (1998-01-01), Moore et al.
patent: 5733711 (1998-03-01), Juengling
patent: 5852497 (1998-12-01), Pramanik et al.
patent: 5982044 (1999-11-01), Lin et al.
patent: 6239031 (2001-05-01), Kepler et al.
Jeffrey P. Hebb and Klavs F. Jensen,The Effect of Patterns on Thermal Sress During Rapid Thermal Processing of Silicon Wafer, IEEE Transaction on Semiconductor Manufacturing, vol. II, No. 1, Feb. 1998.
Hatab Ziad R.
Holscher Richard D.
Wright David Q.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Graybill David E.
Micro)n Technology, Inc.
LandOfFree
Automated combi deposition apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automated combi deposition apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automated combi deposition apparatus and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2852611