Automated circuit design dimension change responsive to low...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C430S005000

Reexamination Certificate

active

07735056

ABSTRACT:
The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first target dimension. In one embodiment, the method comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity so as to result in a low contrast condition, selecting a second target dimension that will avoid the low contrast condition if the low contrast condition will result, and forming the phase pattern for an integrated circuit feature having the second target dimension. Systems for forming phase patterns and photomasks comprising the phase patterns of the present application are also disclosed.

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Ashton, Robert A., Test Structures for Evaluating Strong Phase Shift Lithography, IEEE Transactions on Semiconductor Manufacturing, vol. 15, No. 2, May 2002, pp. 195-200.

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