Automated approach to constraint generation in IC design

Details Automated approach to constraint generation in IC design Automated approach to constraint generation in IC design

2005-04-05

2005-04-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06877139

ABSTRACT:
A software-based system for generating timing constraints for a proposed IC design has a first input as a synthesizable description of the proposed IC, a second input as a clock specification for the proposed IC, and a processing unit accepting the first and second inputs, and determining therefrom as an output, a set of timing constraints to guide implementation of the proposed IC design.

REFERENCES:
patent: 5896299 (1999-04-01), Ginetti et al.
patent: 6658628 (2003-12-01), Landy et al.
U.S. Provisional application No. 60/365,749, Ajay Janami Daga.

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