Autoaligned etching process for realizing word lines in memory d

Details Autoaligned etching process for realizing word lines in memory d Autoaligned etching process for realizing word lines in memory d

1997-12-23

2000-10-10

Chaudhuri, O.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438696, H01L 21311

Patent

active

061301655

ABSTRACT:
Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

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S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, Lattic Press, p. 553, 1986.

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