Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-05-24
2005-05-24
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S012000, C714S048000
Reexamination Certificate
active
06898732
ABSTRACT:
A computing device having multiple masters. The device includes a set of masters and at least one target with at least one bus that provides connecting between the masters and the target. A system controller operates to quiesce masters selected from the set of masters in response to an error message. A system error processor handles the error condition after the selected masters have been quiesced.
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Forman James
Sukavanam Venkataraman
Trehus Eric Mathew
Beausoliel Robert
Cisco Technology Inc.
Johnson & McCollom, P.C.
Wilson Yolanda L
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