Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-05
2008-09-16
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C710S110000, C710S113000, C710S317000
Reexamination Certificate
active
07426709
ABSTRACT:
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bus should be used. In one embodiment, a latency constraint is used to determine whether a lower latency design with arbitration logic at the slave modules is to be used. In one embodiment, throughput constraints are used to determine whether a higher throughput design with arbitration logic at the slave modules is to be used.
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Cuenot Kevin T.
O'Malley Joseph P.
Rossoshek Helen
Ward Thomas A.
Xilinx , Inc.
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