Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-09-16
2008-09-16
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C710S110000, C710S113000, C710S317000
Reexamination Certificate
active
11198785
ABSTRACT:
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bus should be used. In one embodiment, a latency constraint is used to determine whether a lower latency design with arbitration logic at the slave modules is to be used. In one embodiment, throughput constraints are used to determine whether a higher throughput design with arbitration logic at the slave modules is to be used.
REFERENCES:
patent: 5915102 (1999-06-01), Chin
patent: 6034542 (2000-03-01), Ridgeway
patent: 6243829 (2001-06-01), Chan
patent: 6467010 (2002-10-01), Pontius et al.
patent: 6507243 (2003-01-01), Harris et al.
patent: 6665855 (2003-12-01), Payne et al.
patent: 6779170 (2004-08-01), Montrym
patent: 6785755 (2004-08-01), Holm et al.
patent: 6917998 (2005-07-01), Giles
patent: 6959428 (2005-10-01), Broberg et al.
patent: 6968514 (2005-11-01), Cooke et al.
patent: 6978397 (2005-12-01), Chan
patent: 7007121 (2006-02-01), Ansari et al.
patent: 7076595 (2006-07-01), Dao et al.
patent: 7130942 (2006-10-01), Gemelli et al.
patent: 7183796 (2007-02-01), Leijten-Nowak
patent: 7246185 (2007-07-01), Pritchard et al.
patent: 7266632 (2007-09-01), Dao et al.
patent: 7310594 (2007-12-01), Ganesan et al.
patent: 2003/0204831 (2003-10-01), Payne et al.
Hwang et al.; “An improved implementation method of AHB BusMatrix”; Sep. 25-28, 2005; SOC Conference, 2005. Proceedings. IEEE International; pp. 211-214.
Pelgrims, Patrick et al., “Embedded Systeemontwerp op basis van Soft-en Hardcore FPGA's”,AMBA Avalon CoreConnect Wishbone, pp. 1-6, v 1.1, available from De Nayer Instituut, J. De Nayerlaan 5, B-2860 Sint-Katelijne-Waver, Tel. (015) 31 69 44.
Cuenot Kevin T.
O'Malley Joseph P.
Rossoshek Helen
Ward Thomas A.
Xilinx , Inc.
LandOfFree
Auto-generation and placement of arbitration logic in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Auto-generation and placement of arbitration logic in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Auto-generation and placement of arbitration logic in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3917691