Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2001-09-04
2004-06-22
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C365S225700
Reexamination Certificate
active
06753718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a semiconductor device and, more particularly, to an auto fusing circuit for automatically performing fusing operations with a single application of a fuse enable signal.
2. Description of the Related Art
If a fusing operation is performed using a serial interface, then conventionally the fusing operation is performed by selecting a bit having a different logic value from a first specific logic value, and a fusing operation of the next bit is performed after waiting a predetermined time for completion of the first fusing operation. Here, if the number of bits on which the fusing operation will be performed is N, then it takes N multiplied by the performance time of a single fusing operation for performing the N fusing operations.
FIG. 1A
is a circuit diagram illustrating a conventional fusing cell. The conventional fusing cell of
FIG. 1A
includes inverters
11
and
12
connected in series, a bipolar transistor (N
1
) connected in series between a source voltage (VDD) and an earth voltage (VSS), and a fuse (FU).
Describing the operation of the conventional fusing cell of
FIG. 1
a
further, the inverters
11
and
12
receive a fuse enable signal (FEN), and apply the signal to a base of the bipolar transistor (N
1
). If the fuse enable signal (FEN) is at a logic high level, then the bipolar transistor (N
1
) turns on, a collector current (IC) is applied to the fuse (FU), and the fusing operation is performed.
FIG. 1B
is a timing diagram illustrating the fusing operation of the fusing cell of FIG.
1
A. If the fuse enable signal (FEN) is at the logic high level, then the bipolar transistor (N
1
) turns on, and the collector current (IC) is activated at the logic high level. Then, after a time of tO passes, the fusing operation is completed, and the collector current (IC) becomes logic low level.
If there are N fusing cells, and each of the fusing cells are fused, the fuse enable signal (FEN) is applied at the logic high level, and after waiting a time of tO, the fuse enable signal (FEN) of the next fusing cell is activated at the logic high level. Therefore, if the fusing operation is performed on all N fusing cells, the fusing operation takes N×tO, and fusing cells which perform fusing operations with the serial interface must be controlled every time.
SUMMARY OF THE INVENTION
To solve the above and other related problems of the prior art, there is provided an auto fusing circuit, in which fusing operations are sequentially performed with a single application of fuse enable signal, and a test time is reduced.
According to an aspect of the present invention, there is provided an auto fuse circuit. A primary fuse block receives a fuse enable signal as an enable signal, and performs a fusing operation. A plurality of secondary fuse blocks connected to an output terminal of the primary fuse block in series respectively receive an output signal of a previous fuse block as the enable signal, and sequentially perform fusing operations.
According to another aspect of the present invention, the primary fuse block and each of the plurality of secondary fuse blocks comprise logical multiplying means for logically multiplying the enable signal and a corresponding one of the select signals. A fusing cell block performs a fusing operation in response to an output signal of the logical multiplying means. A multiplexer selects one of an output signal of the fusing cell block and the enable signal as a fuse block output signal in response to the corresponding one of the select signals.
Therefore, the auto fusing circuit according to the present invention has advantages in that the fusing operations are sequentially performed with a single application of a fuse enable signal, and a test time can be reduced.
REFERENCES:
patent: 4125880 (1978-11-01), Taylor
patent: 4937465 (1990-06-01), Johnson et al.
patent: 5293339 (1994-03-01), Suzuki et al.
patent: 5424672 (1995-06-01), Cowles et al.
patent: 5610865 (1997-03-01), Shin et al.
patent: 5933376 (1999-08-01), Lee
patent: 6014052 (2000-01-01), Coupe, II
patent: 6246243 (2001-06-01), Audy
F. Chau & Associates LLC
Lam Tuan T.
Samsung Electronics Co,. Ltd.
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