Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-17
2002-07-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06425112
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to modeling of integrated circuit layouts and more particularly to an improved process for checking for and correcting design rule violations.
2. Description of the Related Art
Conventional integrated circuit design rule checking systems check designed shapes against a complicated set of rules. More recently, design rule checking systems have begun to utilize commercial programs (such as those by Numerical Technologies, Inc., 333 West Maude Ave., Suite 207, Sunnyvale, Calif., U.S.A.), which model many of the diffraction induced phenomena and subsequently use the modeled wafer image as the input to a design rule checker. This approach simplifies the coding of the design rule checker since the complexities of the diffraction phenomena are accounted for in the wafer image modeling program. However, such conventional approaches do not account for photolithographic or other process effects on the net process window.
As the minimum feature size in semiconductor integrated circuit technology is pushed below the wavelength of the light used to transfer the mask images to the wafers, diffraction effects introduce the need for additional complex design rules. In addition, other physical effects such as localized etch variations, mask distortions, lens distortions, and topography related effects introduce deviations between the desired and actual printed patterns on the wafer. These effects become increasingly important as the physical dimensions of the circuit elements decrease. These complexities make it difficult both to do the design layout and the design rule checking (DRC) correctly.
FIG. 1A
is a flowchart of a prior art design checking program and
FIG. 1B
illustrates shapes correlating to the flowchart in FIG.
1
A.
Input from the design manual
10
is used to create a design data set
11
which forms the first set of shapes
16
. Next, optical proximity correction and/or phase shift mask adjustment programs add notches and bars
18
or other changes to the initial set of shapes
16
to reduce the anticipated distortion which occurs during the manufacturing process to produce the shapes shown as items
17
in FIG.
1
B.
A simulation program produces the wafer image
19
as shown in block
13
. The simulated manufactured image
19
usually has rounded comers, and other distortions. Next a design rule check
14
is performed to determine, for example, if the space A (e.g., the space between the images
19
) is within the range specified in the design rules. If the space A violates a design rule it would be flagged and identified on an errorlist
15
.
The conventional approaches do not explore the effects of process variations such as focus, exposure, overlay, etc., in determining whether the shapes obey the design rules. Conventional systems utilize very complicated rule sets, have an approach limited to nominal processing quality, and do not account for real world manufacturing complications.
Further, the process window variation ultimately is a key factor in determining the manufacturability of the design. The present state of the art entails running the checker, finding errors, and then manually modifying the design in an attempt to fix the errors. Because some of the process effects are non-linear and non-local, the changes required to fix the error can be far from obvious. Presently, fixes may be typically made by either simply adjusting entire edges of existing shapes or moving entire shapes. These fixes do not take into account any of the important but subtle non-linear and non-local effects mentioned above.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method and computer system for checking designs for design rule violations. The method may include generating a working design data set based on the designs, creating an image data set based on the working design data set, comparing the image data set to the design rules and automatically altering the working design data set when the comparing indicates a design rule violation. The method may further automatically repeat the creating, the comparing and the automatically altering until no design rule violations occur or until no solution to the errors exists.
The method may also include adjusting at least one of size, shape and spacings of the working design data set. Further, the wafer image data set may be a predicted printed structure on a wafer and the method may check integrated circuit designs. The design rules may check spacing, intersection area, common run lengths and overlapping. Further, the altering may add notches to the working design data set.
This method has the advantage that design rule errors occurring anywhere within the process window will automatically be fixed if possible or flagged as unfixable within the constraints of the existing layout. Even errors caused by complex non-local optical phenomena can be corrected by this method.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
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patent: 5432714 (1995-07-01), Chung et al.
patent: 5631110 (1997-05-01), Shioiri et al.
patent: 5698346 (1997-12-01), Sugawara
patent: 5705301 (1998-01-01), Garza et al.
patent: 5707765 (1998-01-01), Chen
patent: 5723233 (1998-03-01), Garza et al.
patent: 5725974 (1998-03-01), Kawahira
patent: 5740068 (1998-04-01), Liebmann et al.
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patent: 6015644 (2000-01-01), Cirelli
Makers of CATS(tm) Software Computer Aided Transcription System, “Mask and Wafer Image Enhancement Through Advanced Fracture Techniques”, BACUS '97, Sep. 1997, pp. 1-12.
Bula Orest
Cole Daniel C.
Conrad Edward W.
Leipold William C.
Do Thuan
McGinn & Gibb PLLC
Richard M. Kotulak Esq.
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