Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-11
2002-11-19
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06484302
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the placement of contacts for signal lines between layers on an integrated circuit, and more particularly, to an auto-contactor system and method for automatically placing variable size contacts (a.k.a. “vias”) between same named signals on different layers of an integrated circuit chip automatically.
2. Discussion of the Related Art
Integrated circuits (IC) are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip”. These components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. Very large scale integration (VLSI) technology is often utilized to create semiconductor integrated circuits comprising thousands of logic elements and signal lines. VLSI circuits are fabricated on silicon, gallium-arsenide or germanium wafer (i.e., substrate) and typically include signal lines and logic structures.
The logic element structures control the signal processing and comprise irregular elements, such as gates, latches, memory arrays or multipliers. These logic structures are built up on an integrated circuit into multiple layers. In order for each of these logic elements to perform they need inputs and outputs. These inputs and outputs are usually signal lines from other logic elements. These signal lines typically run horizontally on a layer or vertically through a layer. The signal lines that run horizontally in a layer also are typically run orthogonally on one side of the layer as compared to the opposite side of the layer. For example, this means that in adjacent pair of layers the upper layer the signal lines run in one direction, such as in north-south, and then on the lower layer the signal lines would be perpendicular and run east-west. The conductors carry control signals, data signals, clock signals, power (such as VDD) and ground. A hole is created in the insulating material between layers to get these power, ground and signal lines from one layer or another. A contact is then placed in the hole so as to connect conductors on adjacent layers. This allows VDD, ground and data signals to be routed wherever needed on a chip.
The lines for VDD and ground are typically wide lines to reduce resistance. However, the contacts between layers are generally of fixed size. These contacts have a high resistance compared to the conductive lines. That being the case, one typically places multiple fixed size contacts to connect conductors between adjacent layers. It is desirable to have numerous contacts for these power lines in order to minimize resistance.
In general, with regard to generating the design of the VLSI circuits, net lists are generated by various means including extraction from schematics and “artwork” (detailed layouts of components and connecting conductors and contacts). The net list is a listing of all the logic elements and the connectivity of the logic elements that comprise a block of logic. The net list is fed into a placement and routing tool, which generates the layout of the VLSI circuits therefrom. The resulting layout designates the actual position and wiring of each logic element of the VLSI circuits. The degree to which the placement of each component is optimized is a function of the design criteria of the placement and routing algorithm implemented by the placement and routing tool and the amount of central processing unit (CPU) time devoted to the operation of the placement and routing tool.
These algorithms are designed to minimize the routing resistance and capacitance in the VLSI circuits by minimizing the routing lengths between connections. If the routing lengths are minimized, then the routing capacitive load is minimized, and the VLSI circuits is faster, smaller (i.e., denser), and consumes less power, all of which are desirable attributes. Most conventional placement and routing algorithms achieve this optimization via an iterative, pseudo-random placement scheme. After an initial placement of the components, each component is considered for a move to see if the design can be better optimized by the move. The type of moves considered are usually either (1) swapping the position of a component with another randomly selected component, or (2) moving the position of a component to a randomly selected new location. The determination of whether or not the design can be optimized by the move is based upon a cost function. For example, the cost function may be the total wire length of the design, whereby the lower the total wire length, the more optimized the design.
A calculation is done by the algorithm for each move to determine the change in the cost function caused by the proposed move. If the change is negative, thereby generating a new lower cost function, then the move is accepted and used as a new placement for the component under consideration for further iterations of the algorithm. Selecting only negative cost function changes is called a “greedy” algorithm.
A more advanced placement and routing algorithm, referred to as “simulated annealing”, will occasionally accept moves producing a positive change in the cost function. In such cases, the simulated annealing algorithm will either accept or refuse the proposed move based upon the magnitude of a positive change, a decreasing value called the “temperature”, and a random number so that the selection of the move is a probabilistic selection. Thus, a simulated annealing placement and routing algorithm performs design optimization via multiple iterations of a pseudo-random placement scheme modified by a temperature cost function.
While the methods described above and those known in the industry are adequate when placing standard logic elements, such as gates and latches, in the VLSI circuits, they have proven to be inadequate when placing and routing contact elements for wide signal lines between the layers of the IC chip. Simply stated, the current methods known in the industry do not automatically generate contacts between same name signals on different layers of an integrated circuit in an efficient manner. The current methods known in the industry do not adjust the contact density according to the size and shape of the individual areas where contacts from one signal line on one integrated circuit layer can be placed to be in contact with a same name signal line on a different layer while still providing good conductivity between the layers and avoiding the generation of excessive number of contacts which could overwhelm programs which subsequently process the layout data (e.g., DRC, mask generator).
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
To achieve the advantages and novel features, the auto-contactor provides a system and method for optimizing the size and placement of contact elements for connecting signal lines from one layer to another. Briefly described, in architecture, the auto-contactor can be implemented as follows. The contact area mechanism identifies a contact area that overlaps the signal line from the first layer of the integrated circuit and the signal line on the second layer of the integrated circuit. The optimizing mechanism calculates an optimal size of a plurality of contacts in the contact area.
The auto-contactor system of the present invention also provides for and can be thought of as a method that optimizes the placement and size of contact elements for connecting a signal line on a first layer of the integrated circuit to a signal line on a second layer of the integrated circuit that comprises the following steps: (1) identifying a contact area that overlaps the signal line from the first layer of the integrated circuit and the second layer of the integrated circuit; and (2) calculating an optimal size of a plurality of contacts in
Hewlett--Packard Company
Levin Naum
Smith Matthew
LandOfFree
Auto-contactor system and method for generating variable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Auto-contactor system and method for generating variable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Auto-contactor system and method for generating variable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2964041