Authentication chip with protection from power supply attacks

Details Authentication chip with protection from power supply attacks Authentication chip with protection from power supply attacks

2000-03-02

2004-06-01

Morse, Gregory (Department: 2134)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

C347S014000, C347S019000, C347S086000, C347S010000, C347S011000, C347S012000

Reexamination Certificate

active

06745331

ABSTRACT:

TECHNICAL FIELD
This invention concerns an authentication chip including an OverUnderPower detection unit to prevent power supply attacks.
BACKGROUND OF THE INVENTION
The process of authentication has particular application in any system (chip or software) that manipulates secure data. This includes Internet commerce, peer to peer communication, Smart Cards, Authentication chips, electronic keys, and cryptographic equipment. Whilst the description of the preferred embodiments of the present invention assumes a System/consumable relationship, it is a trivial matter to extend the protocol for other uses. An example is Internet commerce, where each consumer is effectively the consumable, and the Shop is the System. Another usage is Smart Cards, where each smart card can have a unique key, known to the System.
Existing solutions to the problem of authenticating consumables have typically relied on physical patents on packaging. However this does not stop inferior refill operations or clone manufacture in countries with weak industrial property protection. Consequently a much higher level of protection is required.
SUMMARY OF THE INVENTION
The invention is an authentication chip including an OverUnderPower detection unit to prevent power supply attacks, the unit comprising: a first comparator having a first input connected to a reference voltage and a second input connected to a power supply line to detect voltage rises above a predetermined limit, and a second comparator having a first input connected to the reference voltage and a second input connected to the power supply line to detect voltage drops below a predetermined limit, and an output to provide a RESET signal to clear all volatile memory in the chip in the event of the power supply voltage exceeding the predetermined limits.
The OverUnderPower Detection Unit detects power glitches and tests the power level against the Voltage Reference to ensure it is within a certain tolerance
The OverUnderPower Detection Unit may be connected into the RESET Tamper Detection Line, to cause a RESET when triggered.
A side effect of the OverUnderPower Detection Unit is that as the voltage drops during a power-down, a RESET is triggered, thus erasing any work registers.
The OverUnderPower Detection unit may be implemented in CMOS.
The OverUnderPower Detection unit may be covered by a tamper detection line, or by a tamper prevention line, or both, so that if an attacker attempts to tamper with the unit, the chip will either RESET or erase all secret information.


REFERENCES:
patent: 3845657 (1974-11-01), Hall et al.
patent: 4001777 (1977-01-01), Alexander
patent: 4509201 (1985-04-01), Sekigawa et al.
patent: 5239575 (1993-08-01), White et al.

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