Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
1997-08-11
2001-06-26
Isen, Forester W. (Department: 2644)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C700S094000
Reexamination Certificate
active
06253303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a signal processing device, and particularly to an audio signal processing circuit which inputs subband samples of audio signals that have been divided and quantized in advance for each frequency band, processes these signals and outputs the results as audio samples.
2. Description of the Related Art:
ISO/IEC 11172-3 contains provisions for the international standards for an expansion circuit for compressed audio signals in such an audio signal processing circuit. An example of the construction of this type of audio signal processing circuit of the prior art is shown in FIG.
1
. The circuit shown in
FIG. 1
carries out a discrete cosine transform (DCT) of the subband signal, combines bands, and generates an audio signal.
This audio signal processing circuit is composed of requantizing circuit
12
; DCT memory
14
for storing DCT samples for discrete cosine transform; DCT circuit
16
for carrying out discrete cosign transforms; band synthesis memory
18
; address generating circuit
44
; band synthesis circuit
20
; and control circuit
43
for controlling the operation of these circuits.
Requantizing circuit
12
requantizes a quantity N (where N is an integer product of 4) of input subband samples
1
, which have been quantized to differing word lengths for each frequency, for every group of 32 samples, and stores the requantized 32 DCT samples
13
in DCT memory
14
.
DCT circuit
16
applies a discrete cosine transform represented by the following formula (1) to DCT samples
15
stored in DCT memory
14
, and stores the 32 band synthesis samples
17
comprising from syn[
0
] to syn[
31
] resulting from the transform into band synthesis memory
18
.
syn
[
k
]
=
∑
i
=
0
31
cos
(
(
2
k
+
1
)
i
π
/
64
)
(
1
)
Address generating circuit
44
generates addresses in band synthesis memory
18
in which band synthesis samples
17
calculated by DCT circuit
16
are stored. Band synthesis memory
18
has a storage area for 512 samples made up of 16 blocks of 32 samples each.
The block for storage of each discrete cosine transform is successively shifted such that, when the first 32 samples resulting from discrete cosine transform are stored in the first block, the next 32 samples resulting from discrete cosine transform are stored in the second block, and when samples have been stored in all 16 blocks, the next results of discrete cosine transform are again stored in the first block.
Band synthesis circuit
20
extracts one sample from each block of data stored in band synthesis memory
18
for each fixed time period determined as the sampling period for a total of 16 samples, carries out a product/sum operation, and outputs the result of this operation as output audio sample
11
for one sample.
Regarding the overall operation of this audio signal processing circuit, when 32 quantized input subband samples
1
are inputted to requantizing circuit
12
, requantizing circuit
12
first requantizes this input and then stores the resulting 32 DCT samples
13
into DCT memory
14
.
DCT circuit
16
carries out the DCT operation on DCT samples
13
stored in DCT memory
14
, and stores the resulting 32 band synthesis samples
17
(from syn[
0
] to syn[
31
]) in one block within band synthesis memory
18
.
Thirty-two output audio samples
11
(from pcm[
0
] to pcm[
31
]) are calculated after the completion of the nth DCT processing and the storage of band synthesis samples
17
in band synthesis memory
18
. For every calculation of one output audio sample
11
, a total of 16 band synthesis samples
19
are extracted, one sample being extracted from each block of band synthesis memory
18
for use in this calculation.
The ith output audio sample pcm[i] of the 32 output audio samples
11
is calculated according by the following formula (2):
if
0
≦
i
<
16
,
then
pcm
n
[
i
]
=
∑
P
=
o
7
(
syn
n
-
2
P
[
i
+
16
]
-
syn
n
-
2
P
-
1
[
16
-
i
]
)
if
i
=
16
,
then
pcm
n
[
i
]
=
∑
P
=
n
7
(
-
syn
n
-
2
P
-
1
[
16
-
i
]
)
if
17
≦
i
≦
31
,
then
pcm
n
[
i
]
=
∑
P
=
n
n
+
7
(
-
syn
n
-
2
P
[
48
-
i
]
-
syn
n
-
2
P
-
1
[
i
-
16
]
)
}
(
2
)
In a case in which band synthesis circuit
20
calculates output audio sample
11
immediately after the results outputted from DCT circuit
16
are stored in band synthesis memory
18
, for example, in a case in which pcm[i] is calculated in order for i=0 to i=31 immediately after the 16th DCT results are stored in block
16
, the band synthesis samples necessary for the calculation are as shown by the half-tone portions in FIG.
2
(
a
).
Next, the band synthesis samples necessary for calculation of pcm[i] of output audio sample
11
immediately after storing the 17th DCT results in band synthesis memory
18
are as shown by the half-tone portions in FIG.
2
(
b
).
At the time of the state shown in FIG.
2
(
a
), the data of from syn[
17
] to syn[
31
] of block
1
will not be used again. Based on formula (2), the memory is vacated successively beginning from syn[
0
] of block
1
after calculating pcm[
16
]. In other words, syn[
0
] is no longer necessary after calculating pcm[
16
], and syn[
1
] is no longer necessary after calculating pcm[
17
]. Processing can be continued by again storing band synthesis samples
19
in these areas that successively become unnecessary.
FIG. 3
is a timing chart showing the relation between the requantizing process, the DCT process, and the synthesizing process, and shows the calculation of 32 output audio samples
11
up to the beginning of the calculation of the next 32 output audio samples.
Band synthesis samples are stored in blocks
1
to
16
of band synthesis memory
18
. With the start of the calculation of pcm[
0
] (
35
in FIG.
3
), requantizing circuit
12
first requantizes input subband samples
1
and stores the results in DCT memory
14
(
36
in FIG.
3
).
At this time, the portions in which from syn[
17
] to syn[
31
] were stored in block
1
of band synthesis memory
18
are vacated, and after calculating pcm[
16
], become vacant in order from syn[
0
] to syn[
1
] to syn[
2
], and so on. DCT circuit
16
therefore proceeds calculating and storing syn[i] in the order of this vacating of the memory (
37
in FIG.
3
).
This configuration of the prior art requires memory for 32 samples in DCT memory
14
(a total of 768 bits if each sample comprises 24 bits) and for 512 samples in band synthesis memory
18
(a total of 12,288 bits).
SUMMARY OF THE INVENTION
In the above-described prior art, the memory capacity required in the band synthesis circuit increases with the increase in the number of samples and with the number of bits making up one sample, and as a consequence, the prior art has the drawbacks of large circuit size and high cost. In view of the above-described problems of the prior art, the object of the present invention is therefore to reduce the amount of memory required in the band synthesis circuit of an audio signal processing circuit.
In order to realize the above-described object, the audio signal processing circuit according to the present invention includes: a requantizing circuit that requantizes a number N of inputted subband samples and generates N DCT samples; a DCT memory in which are stored N DCT samples; a DCT circuit that applies a discrete cosine transform on N DCT samples stored in the DCT memory and generates band synthesis samples; a band synthesis memory having a storage area for storing (M&minu
Isen Forester W.
NEC Corporation
Pendleton Brian
Sughrue Mion Zinn Macpeak & Seas, PLLC
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