Audio device

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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C710S306000, C709S238000

Reexamination Certificate

active

11318601

ABSTRACT:
The present invention provides a digital bus circuit comprising: a bus conductor having two sections each connected to a pass circuit, each bus section being connected to two bus interfaces for respective circuits; at least three of the bus interfaces comprising a tri-state output buffer having a tri-state mode and one or more logic output modes; wherein in a unitary bus mode the tri-state output buffers are arranged such that only one of said output buffers is not in a tri-state mode, and the pass circuit is arranged to substantially couple said bus sections; and wherein in a dual bus mode the tri-state output buffers are arranged such that only one of the output buffers connected to each bus section is not in a tri-state mode, and wherein the pass circuit is arranged to substantially isolate said bus sections.

REFERENCES:
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patent: 5936424 (1999-08-01), Young et al.
patent: 6081863 (2000-06-01), Kelly et al.
patent: 6857039 (2005-02-01), Makino
patent: 7145903 (2006-12-01), Gutierrez
patent: 7231531 (2007-06-01), Cupps et al.
patent: 2004/0041902 (2004-03-01), Washington
patent: 2004/0260983 (2004-12-01), Leung et al.
patent: 0 431 688 (1991-06-01), None
patent: 57-187726 (1982-11-01), None
patent: WO 01/73566 (2001-10-01), None
patent: WO 02/063480 (2002-08-01), None
54LS125A/DM54LS125A/DM74LS125A Quad Tri-State Buffers Data Sheet, National Semiconductor, Jun. 1989, pp. 1-2 (http://rabbit.eng.miami.edu/info/datasheets/74LS125.pdf, accessed Aug. 3, 2007).

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