Atomic memory operators in a parallel processor

Details Atomic memory operators in a parallel processor Atomic memory operators in a parallel processor

2006-09-21

2009-12-01

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

07627723

ABSTRACT:
Methods, apparatuses, and systems are presented for updating data in memory while executing multiple threads of instructions, involving receiving a single instruction from one of a plurality of concurrently executing threads of instructions, in response to the single instruction received, reading data from a specific memory location, performing an operation involving the data read from the memory location to generate a result, and storing the result to the specific memory location, without requiring separate load and store instructions, and in response to the single instruction received, precluding another one of the plurality of threads of instructions from altering data at the specific memory location while reading of the data from the specific memory location, performing the operation involving the data, and storing the result to the specific memory location.

REFERENCES:
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patent: 2002/0174318 (2002-11-01), Stuttard et al.
patent: 2003/0120880 (2003-06-01), Banno
Stokes, Jon, Introduction to Multithreading, Superthreading and Hyperthreading, Oct. 3, 2002, http://arstechnica.com/articles/paedia/cpu/hyperthreading.ars.
S.J. Eggers et al., “Simultaneous Multithreading: A Platform for Next-Generation Processors” IEEE Micro, Sep.-Oct. 1997, p. 12-19.

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