Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-11-22
2004-06-08
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S558000
Reexamination Certificate
active
06746934
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor integrated circuits and, in particular, to an improved method for doping wafers.
BACKGROUND OF THE INVENTION
Incorporation of dopants or chosen impurities into a semiconductor material, commonly known as doping, is well known in the art. Thermal diffusion and ion implantation are two methods currently used to introduce a controlled amount of dopants into selected regions of a semiconductor material.
Doping by thermal diffusion is a two-step process. In the first step, called predeposition, the semiconductor is either exposed to a gas stream containing excess dopant at low temperature to obtain a surface region saturated with the dopant, or a dopant is diffused into a thin surface layer from a solid dopant source coated onto the semiconductor surface. The predeposition step is followed by the drive-in step, during which the semiconductor is heated at high temperatures in an inert atmosphere so that the dopant in the thin surface layer of the semiconductor is diffused into the interior of the semiconductor, and thus the predeposited dopant atoms are redistributed to a desired doping profile.
Ion implantation is preferred over thermal diffusion because of the capability of ion implantation to control the number of implanted dopant atoms, and because of its speed and reproducibility of the doping process. The ion implantation process employs ionized-projectile atoms that are introduced into solid targets, such as a semiconductor substrate, with enough kinetic energy (3 to 500 KeV) to penetrate beyond the surface regions. A typical ion implant system uses a gas source of dopant, such as, BF
3
, PF
3
, SbF
3
, or AsH
3
, for example, which is energized at a high potential to produce an ion plasma containing dopant atoms. An analyzer magnet selects only the ion species of interest and rejects the rest of species. The desired ion species are then injected into an accelerator tube, so that the ions are accelerated to a high enough velocity to acquire a threshold momentum to penetrate the wafer surface when they are directed to the wafers.
Although ion implantation has many advantages, such as the ability to offer precise dopant concentrations, for example, for silicon of about 10
14
to 10
21
atoms/cm
3
, there are various problems associated with this doping method. For example, a major drawback for ion implantation is the radiation damage, which occurs because of the bombardment involved with heavy particles and further affects the electrical properties of the semiconductor. The most common radiation damage is the vacancy-interstitial defect, which occurs when an incoming dopant ion knocks substrate atoms from a lattice site and the newly dislocated atoms rest in a non-lattice position. Further, most of the doping atoms are not electrically active right after implantation mainly because the dopant atoms do not end up on regular, active lattice sites. By a suitable annealing method, however, the crystal lattice could be fully restored and the introduced dopant atoms are brought to electrically active lattice sites by diffusion.
Ion channeling is another drawback of ion implantation that could also change the electrical characteristics of a doped semiconductor. Ion channeling occurs when the major axis of the crystal wafer contacts the ion beam, and when ions travel down the channels, reaching a depth as much as ten times the calculated depth. Thus, a significant amount of additional dopant atoms gather in the channels of the major axis. Ion channeling can be minimized by several techniques, such as employing a blocking amorphous surface layer or misorienting the wafer so that the dopant ions enter the crystal wafer at angles different than a 90° angle. For example, misorientation of the wafer
3
to 7° off the major axis prevents the dopant ions from entering the channels. However, these methods increase the use of the expensive ion-implant machine and, thus, could be very costly for batch processing.
Another disadvantage of the conventional doping methods is the autodoping. After dopants are incorporated into a crystalline wafer to form various junctions, they undergo many subsequent processing steps for device fabrication. Although efforts are made to use low-temperature processing techniques to minimize redistribution of incorporated dopant atoms, the dopants still redistribute during the course of further processing. For example, this redistribution of dopants becomes extremely important when an epitaxial film is grown over the top of the doped area, particularly because of the high temperature required for epitaxial growth. At high temperatures, the dopant diffuses into the growing epitaxial film during the epitaxial growth, and this phenomenon is referred to as autodoping. This phenomenon also leads to unintentional doping of the film in between the doped regions, or into the nondiffused substrate. For this, integrated circuit designers must leave adequate room between adjacent regions to prevent the laterally diffused regions from touching and shorting.
Furthermore, current doping systems today employ a batch processing, in which wafers are processed in parallel and at the same time. An inherent disadvantage of batch processing is cross contamination of the wafers from batch to batch, which further decreases the process control and repeatability, and eventually the yield, reliability and net productivity of the doping process.
Accordingly, there is a need for an improved doping system, which will permit minimal dopant redistribution, precise control of the number of implanted dopants, higher commercial productivity and improved versatility. There is also needed a new and improved doping system and method that will eliminate the problems posed by current batch processing technologies, as well as a method and system that will allow greater uniformity and doping process control with respect to layer thickness necessary for increasing density of integration in microelectronics circuits.
SUMMARY OF THE INVENTION
The present invention provides an improved method and unique atomic layer doping system and method for wafer processing. The present invention contemplates an apparatus provided with multiple doping regions in which individual monolayers of dopant species are first deposited by atomic layer deposition (ALD) on a wafer and then the respective dopants are diffused, by thermal reaction, for example, into the wafer surface. Each doping region of the apparatus is chemically isolated from the other doping regions, for example, by an inert gas curtain. A robot is programmed to follow pre-defined transfer sequences to move wafers into and out of respective doping regions for processing. Since multiple regions are provided, a multitude of wafers can be simultaneously processed in respective regions, each region depositing only one monolayer dopant species and subsequently diffusing the dopant into the wafer. Each wafer can be moved through the cycle of regions until a desired doping concentration and profile is reached.
The present invention allows for the atomic layer doping of wafers with higher commercial productivity and improved versatility. Since each region may be provided with a pre-determined set of processing conditions tailored to one particular monolayer dopant species, cross contamination is also greatly reduced.
These and other features and advantages of the invention will be apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.
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patent: 5298542 (1994-03-01), Mayerson
patent: 5310698 (1994-05-01), Wild
patent: 5527733 (1996-06-01), Nishizawa et al.
patent: 5793109 (1998-08-01), Nakamura
patent: 5916365 (1999-06-01
Doan Trung T.
Sandhu Gurtej
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Mulpuri Savitri
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