Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-05-23
2002-09-10
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C716S030000
Reexamination Certificate
active
06448096
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to testing and defect analysis of semiconductor dies signal acquisition.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual dies are functional, it is also important to ensure that batches of dies perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. Directly accessing the circuitry is difficult for several reasons. For instance, in flip chip type dies, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
One particular type of semiconductor device structure that presents unique challenges to back side circuit analysis is silicon-on-insulator (SOI) structure. SOI involves forming an insulator, such as an oxide, over bulk silicon in the back side of a semiconductor device. A thin layer of silicon is formed on top of the insulator, and is used to form circuitry over the insulator, and additional circuitry is formed over the thin layer of silicon. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation. Direct access to circuitry for analysis of SOI structure, however, involves milling through the oxide. The milling process can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render the analysis inaccurate. In addition, the milling process can be time-consuming, difficult to control, and thus expensive.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies involving SOI structure.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for analyzing a semiconductor die having silicon-on-insulator (SOI) structure in a manner that overcomes the above-discussed impediments. The die includes a back side opposite circuitry in a circuit side, and the die analysis involves acquiring a signal from the circuitry via the insulator of the SOI structure. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having SOI structure and a back side opposite circuitry in a circuit side is analyzed. A thinned portion of the back side of the die is scanned with an atomic force microscope. The microscope responds to an electrical characteristic of the circuitry coupled to the microscope via the insulator portion of the SOI structure, and the response is used to detect an electrical characteristic of the circuitry.
According to another example embodiment of the present invention, a system is arranged for analyzing a semiconductor die having silicon-on-insulator (SOI) structure and a back side opposite circuitry in a circuit side. The system includes an atomic force microscope adapted to scan a thinned back side of the die and detect a response to the die. A detection arrangement is adapted to use the response of the microscope to detect an electrical characteristic of the circuitry.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 6146014 (2000-11-01), Bruce et al.
patent: 6199563 (2001-03-01), Uehara et al.
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Ring Rosalinda M.
Stone Daniel L.
Advanced Micro Devices , Inc.
Thompson Craig
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