Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-01-31
2003-09-23
Sparks, Donald (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S001000, C711S157000, C365S233500, C365S185170, C365S222000
Reexamination Certificate
active
06625706
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to memory devices, and in particular, to an interleaved memory readable in a synchronous mode or in a random access asynchronous mode with fast access times. The interleaved memory is readable in the synchronous mode by successive locations with a sequential type of access, commonly referred to as a burst mode.
BACKGROUND OF THE INVENTION
In a standard non-volatile memory, a read cycle spans from a request of data by way of the switching of the input address lines to the final extraction of the bits stored in the addressed memory location. In particular, in modern devices, the read circuitry (references, sense amplifiers, etc.) is disabled at the end of each read cycle in order to minimize energy consumption. Therefore, the start of a new reading must be triggered by the generation of a suitable signal (Address Transition Detection pulse or briefly ATD) that is generally produced by a circuit sensing a change of the input address.
A typical ATD pulse generator is depicted in FIG.
1
. The ATD pulse must satisfy fundamental requirements for a correct reading and for satisfying the access time requirements. In fact, independent from the particular architecture of the read circuitry, the ATD must be generated as quick as possible in order to quickly restart the whole analog sensing networks.
That is why it is important to generate the ATD immediately after the input buffer of the address bits. In this way, the time required for the address bits to propagate through the decoding circuitry down to select the addressed cells is simultaneously exploited to re-establish the bias conditions for an optimal reading. It should be noted that the assumption from outside of a new address and the consequent generation of a new ATD before a previous access is finished, causes interruption and suppression of the previously started read cycle and the immediate start of a new read cycle. This superimposes to the first one, thus substituting it.
In “burst” memory devices, i.e., operating in a sequential reading mode, only the first reading, whose address is not predictable, must follow a standard data path. On the contrary, for successive cycles it is necessary to follow a different path. Unlike a standard memory, in a synchronous memory the addresses successive to the first one of random access (asynchronous) are internally generated by a counter incremented by a pulse coherently with the system's clock.
In particular, in a synchronous memory device it is necessary to start the sequential reading, successive to the first reading, and synchronize it by internally generating the addresses, which is updated in a sequential manner. A common ATD pulse generator is unsuitable because the external address lines do not switch (or are not accessible to the memory device) during synchronous read cycles.
It is also true that if a generic signal, untied from the internal address being generated, was used for starting sequential readings, the sensing circuit would become independent from the decoding circuitry. This would run the risk of anticipating or delaying the start of the reading with respect to the correct selection of the memory cells to be sensed.
In order to avoid the problem, at the start of the sequential accesses, the eventual propagation of the internally generated addresses (by introducing an appropriate delay) could be waited for. But in doing so, besides the cost in terms of silicon area required for such a delay chain, the control logic of the sense-amp would be greatly complicated because it will be necessary to implement two alternative data streams for the two different kinds of access: a random-asynchronous mode and a sequential-synchronous mode.
A different approach could be that of placing the ATD generation circuit in cascade of the counter that generates the internal addresses, instead of in cascade of the input address buffer. This is done to always generate the pulses at the same point of the control chain, independently of the kind of access in progress. During the asynchronous reading the counter works as a register because the internal and external addresses coincide.
Unfortunately, this approach burdens the read path in an opposite manner because instead of starting the logic chain when a new reading has been acquired (because a change of address having been detected downstream of the input buffers), it is necessary to wait for the propagation of the signals through the latches of the counter. This increases the total access time.
SUMMARY OF THE INVENTION
In view of the foregoing background, the present invention provides an approach using an ATD signal even for starting sequential readings, by causing its generation when the start of a new cycle of synchronous readings with sequential access is detected.
The most appropriate signal to provide such information is the increment pulse for the internal address counter. In fact, by detecting this increment pulse it is possible to generate a pseudo ATD signal, i.e., stimulated by an internal cause and not by the switching of the external address lines. This starts a new reading.
The final architecture maintains the classical structure of ATD generation, with circuits sensing the external address lines (useful for all conventional accesses) and sensing the pulses of sequential increment of an internal address counter, and generating the ATD pulses for starting sequential readings.
Finally, the two kinds of ATD pulses, a first kind due to external cause and the other kind due to internal cause can be summed by a logic output OR gate of the ATD generator. Therefore, the method of the invention for synchronizing the start of sequential readings for a read cycle of a memory in burst synchronous mode includes using the increment pulses of the address counter, or of the address counters in the case of interleaved memory devices, as synchronization signals, by generating after each increment pulse a dummy ATD pulse. The dummy ATD pulse is practically undistinguishable from an ATD pulse generated by an effective switching of the input address latches.
According to an aspect of the memory architecture of the present invention, an ATD pulse generator conventionally sensing the external address lines is used, but modified to include at least a pulse generator circuit stimulated by an increment pulse synchronized by a respective address counter.
According to a preferred embodiment, in the case of an interleaved memory, the method of the invention can advantageously contemplate the fact that the increment pulses are distinct for the counter of one of the banks of the array of cells of the interleaved memory. The distinct increment pulses produced corresponds to distinct dummy ATD pulses for starting sequential readings in the respective subdivided banks of the array of cells of the interleaved memory.
An external protocol signal (ALE), or more generally, an equivalent command ENABLE for enabling the input latch or latches of acquisition of external input addresses determines, as a function of its logic state, the generation of ATD pulses common to both the subdivided banks of the matrix (array) of cells of the interleaved memory. This is done for read cycles in a random access asynchronous mode or, according to the invention, the generation of dummy ATD pulses specifically for one of the subdivided banks of the matrix of cells of the interleaved memory for a synchronous read cycle in burst access.
The ALE signal establishes that it is necessary to start a read cycle from an external address. For such a cycle, either the first random cycle of a sequence of burst readings or a generic asynchronous access, the ATD pulse stimulated by the switching of the external address lines is sent to all the banks, which will then enable their respective read structures.
If the access were purely asynchronous, both banks will terminate the readings, but only the bank effectively addressed by the external address shall output its data. Bank priority is defined by the least significant bit A<
Campanale Fabrizio
De Ambroggi Luca Giuseppe
Kumar Promod
Nicosia Salvatore
Tomaiuolo Francesco
Jorgenson Lisa K.
Namazi Mehdi
Sparks Donald
STMicroelectronics S.r.l.
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