Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2002-06-24
2004-08-03
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S100000, C710S052000
Reexamination Certificate
active
06772311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to Advanced Technology Attachment Packet Interface (ATAPI) device data transfer, and more particularly to a system and method for allowing an ATAPI device to accommodate both unaligned and aligned parallel I/O data transfers.
2. Description of the Prior Art
An AT Attachment Packet Interface (ATAPI) for CD-ROMs is an extension of the ATA Interface that supports connection of CD-ROM players and tape players to personal computers. The ATAPI Standard (SFF-8020i) defines a Task File, a set of registers used by the peripheral devices and personal computer, used to transfer data. According to ATAPI, commands are communicated using packets. Generally described, a packet is a portion of a message, that may include many packets. Typically, each packet includes destination information and data, or a payload. A packet may also include a packet ID (PID), data, that forms the packet payload, and a cyclical redundancy check (CRC). Because each packet of a message includes a PID, packets need not be transmitted in order to successfully reconstruct the message. Many protocols using packets support isochronous data transfer, as compared to synchronous data transfer. Isochronous data transfer enables video data to be transmitted as quickly as it is displayed and generally supports very high data transfer rates.
ATAPI devices are however, only required to support aligned parallel I/O (PIO) data transfers since the ATAPI standard does not support unaligned PIO data transfers. The ATAPI standard allows only the last DRQ data transfer to have an odd byte count, while necessitating that all other DRQ data transfers have an even byte count in order to avoid unaligned PIO data transfers.
Unaligned PIO data transfer capability allows users to bundle several arbitrary byte count transfers into a single command transaction. This is desirable since multiple command transactions would otherwise be required whenever there is an odd byte count transfer. Known solutions to the foregoing problem have either prohibited unaligned data transfers or have used firmware to move data to or from ATAPI devices whenever the logic detected unaligned data transfers, which has degraded data transfer performance whenever unaligned data transfers occurred.
It is therefore advantageous and desirable in view of the foregoing, to provide a method and system of implementing unaligned PIO data transfer capability to improve ATAPI device system performance by reducing command overhead. Such a method and system would provide a desirable feature for ATAPI device host controllers.
SUMMARY OF THE INVENTION
The present invention is directed to a controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.
According to one embodiment, a parallel input/output data transfer controller comprises a sector FIFO in simultaneous communication with a host device and an ATAPI device; and an ATAPI data buffer controller, wherein the ATAPI data buffer controller is configured to control sector FIFO read and write operations such that the sector FIFO communicates simultaneously with the host device via a host data bus and with the ATAPI device via an ATAPI device bus.
REFERENCES:
patent: 5167551 (1992-12-01), Davis
patent: 5661848 (1997-08-01), Bonke et al.
patent: 6609167 (2003-08-01), Bastiani et al.
patent: 6636922 (2003-10-01), Bastiani et al.
patent: 6697885 (2004-02-01), Goodfellow
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