ATAPI command receiving method

Details ATAPI command receiving method ATAPI command receiving method

2001-02-20

2004-02-03

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S001000, C710S052000, C710S053000, C710S057000, C710S062000, C710S064000, C710S072000, C710S074000, C711S152000, C711S153000, C711S169000, C711S173000, C712S001000, C712S225000

Reexamination Certificate

active

06687763

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a command receiving method of a LSI which controls an ATAPI (AT Attachment Packet Interface) protocol and, more particularly, to an ATAPI command receiving method which can reduce a processing time of a CPU.
BACKGROUND OF THE INVENTION
ATAPI is a standard which is created by that the ATA standard for an interface between a host computer and an integral hard disk is expended for use in multi-media devices, and details thereof are determined by the X3T13 Committee.
Hereinafter, the prior art ATAPI command receiving method is described with reference to
FIGS. 5 and 6
.
FIG. 5
shows a structure where devices
3
~
6
are connected to a host computer
1
via ATA buses
2
.
The devices
3
~
6
are devices for supporting the ATA protocol or devices for supporting the ATAPI protocol. Here, assume that these devices are the devices supporting the ATAPI protocol. As shown in
FIG. 6
, the device
3
comprises a LSI (ATAPI protocol control LSI)
31
for controlling the ATAPI protocol, a CPU
32
for decoding a command received from the host computer
1
and executing a processing in accordance with the command, and a RAM
33
which is accessed by the CPU
32
.
FIG. 6
further shows the structure of the device
3
which is accessed via the ATA bus
2
and the flow of command data. To be more specific, the ATAPI protocol control LSI
31
controls the ATAPI protocol via the ATA bus
2
, the CPU
32
controls the device
3
, and the RAM
33
is accessed by the CPU
32
.
The ATAPI protocol control LSI
31
comprises a shared register storage area
311
for accessing the host computer
1
, and a buffer memory
312
which can be used as a RAM of the CPU
32
.
The shared register storage area
311
contains an ATAPI-protocol-defined command register
3111
, a data FIFO (First in First out)
3112
for temporarily storing command packets or access data which are issued from the host computer
1
to data registers of shared registers, and an other shared register
3113
.
A description is given of the ATAPI command receiving method in the device
3
having the above-mentioned structure in the case where the host computer
1
selects the device
3
among the devices
3
~
6
and issues a command to the device
3
via the ATA bus
2
.
The host computer
1
accesses the shared register storage area
311
of the device
3
selected from the devices
3
~
6
which are connected to the host computer
1
, via the ATA bus
2
, and transmits one-byte command and a batch of commands (hereinafter, referred to as “a command packet”) to the shared register storage area
311
. Here, the command packet is an expanded function of the ATA protocol, and it is plural-byte command data which are set by an exchange of a command (IDENTIFY PACKET DEVICE command) between the host computer
1
and the device
3
when the host computer
1
is activated.
When the command according to the ATAPI protocol is issued from the host computer
1
to the device
3
via the ATA bus
2
, the ATAPI protocol control LSI
31
stores a value of the command register accessed by the host computer
1
into the command register
3111
in the shared register storage area
311
, a value of the command packet accessed by the host computer
1
into the data FIFO
3112
in the shared register storage area
311
, and values of other shared registers accessed by the host computer
1
into the other shared register
3113
in the shared register storage area
311
, respectively, and then outputs an interruption signal to the CPU
32
.
When the CPU
32
receives the interruption signal, it starts interrupt processing routine, accesses the command register
3111
, the data FIFO
3112
or the other shared register
3113
in the ATAPI protocol control LSI
31
, in the interrupt processing routine, and stores the values stored therein in the RAM
33
.
When the CPU
32
finishes the interrupt processing routine, it returns to a command processing routine as the normal process, extracts the stored values from the RAM
33
in the command processing routine, and executes the command processing.
As described above, in the prior art ATAPI command receiving method, when the command is received, the CPU
32
recognizes the interruption from the ATAPI protocol control LSI
31
, accesses the shared register storage area
311
of the ATAPI protocol control LSI
31
in the interrupt processing routine of the CPU
32
, and stores the values of the shared register in the RAM
33
.
However, in the prior art ATAPI command receiving method, much time is spent by the CPU
32
to capture the value of the shared register, which is held by the ATAPI protocol control LSI
31
, in the interrupt processing routine of the CPU
32
, and thereby the other processings by the CPU
32
are adversely delayed.
In addition, when the ATAPI protocol control LSI
31
receives the next command or command packet from the host computer
1
while the CPU
32
is capturing the value of the command register or value of the command packet, there is a risk that the command register value or command packet value which is being captured by the CPU
32
should be destroyed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an ATAPI command receiving method which can reduce the time for the interruption processing by the CPU and increase the stability of the system.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a 1st aspect of the present invention, there is provided a command receiving method in a device which comprises an LSI having a shared register storage area and a buffer memory and controlling an ATAPI (AT Attachment Packet Interface) protocol, and a CPU for executing control of the device having the LSI, and in the command receiving method, when a command is transmitted to the device from a host computer outside the device via an ATA bus, a shared register value stored in the shared register storage area is stored at a storage destination address in the buffer memory which is designated by the CPU, when the CPU gives a data storage permission to the LSI. Therefore, a reduction in the processing time due to elimination in capturing the shared register value by the CPU in the interrupt processing as well as an increase in the stability of the system can be attained. Further, because the LSI can hold the command overwritten by the host computer without the intervention of the CPU and the CPU can designate the address to be stored in the buffer memory, plural sets of commands can be stored at arbitrary positions. Accordingly, it is easily possible to correspond to the overlapping function of the ATAPI protocol.
According to a 2nd aspect of the present invention, there is provided a command receiving method in a device which comprises an LSI having a shared register storage area and a buffer memory and controlling an ATAPI (AT Attachment Packet Interface) protocol, and a CPU for executing control of the device having the LSI, and in the command receiving method, when a command is transmitted to the device from a host computer outside the device via an ATA bus, a value stored in the shared register storage area is stored at a first storage destination address in the buffer memory which is designated by the CPU, when the CPU gives a data storage permission to the LSI, and the value stored in the shared register storage area is stored at a second storage destination address in the buffer memory which is designated by the CPU, when the CPU does not give a data storage permission to the LSI. Therefore, the reduction in the processing time due to the elimination in capturing the shared register value by the CPU in the interrupt processing and the increase in the stability of the system can be attained.
According to a 3rd aspec

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