Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-05-30
2000-10-03
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
710 61, 711150, G06F 1200
Patent
active
061287156
ABSTRACT:
A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.
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Ho Ngo Thanh
Wang Chi-Lie
3Com Corporation
Portka Gary J.
Yoo Do Hyun
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