Asynchronous transfer mode (ATM) segmentation and reassembly uni

Details Asynchronous transfer mode (ATM) segmentation and reassembly uni Asynchronous transfer mode (ATM) segmentation and reassembly uni

1996-07-01

1999-11-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, 711205, 711206, 711207, G06F 1210

Patent

active

059833327

ABSTRACT:
An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

REFERENCES:
patent: 5784708 (1998-07-01), Bridges
O'Donoghue et al., A Buffer Management Scheme for an Ethernet Local Area Network, IEEE Southeastcon '87 . . . vol. 1, Apr. 5, 1987, U.S., p. 164.
Boggs J K , Minimizing Input/Output Page Pinning in a Virtual Storage Data Processor, IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1, 1976, p. 83/84.

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