Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Particular node for directing data and applying cryptography
Reexamination Certificate
1998-07-29
2002-07-23
Peeso, Thomas R. (Department: 2132)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Particular node for directing data and applying cryptography
C713S160000
Reexamination Certificate
active
06425080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a descrambling circuit, in particular, to a descrambling circuit for an ATM (Asynchronous Transfer Mode) cell.
2. Description of the Related Art
In a conventional ATM transmission system, an ATM cell scrambling circuit is used so as a receiving terminal to synchronize a sequential cell as a cell synchronization, and scrambled information is descrambled by an ATM cell descrambling circuit that accords with a standard such as “Self-synchronizing scrambler”, ANSI T1. 646-1995 11.3.
FIG. 5
shows the structure of a cell descrambling circuit block. With reference to
FIG. 5
, the operation of the cell descrambling circuit block
1
will be described. Referring to
FIG. 5
, a scrambled ATM cell sequence
101
and a cell header signal
103
that synchronizes with the ATM cell sequence
101
and that is extracted by a cell synchronizing circuit (not shown) are input to a cell descrambling circuit
2
. When a cell synchronizing condition of the scrambled ATM cells is synchronized fully or is pre-synchronized, the cell descrambling circuit
2
descrambles the scrambled ATM cell sequence
101
except for timing data thereof represented by the cell header signal
103
corresponding to self-synchronizing scrambling method using generating polynomial X
43
+1. The cell descrambling circuit
2
outputs the result as a descrambled ATM cell sequence
102
. A self-synchronizing scrambler “multiplies input data by the term of the maximum degree of a generating polynomial and divides the result by the generating polynomial”. In other words, the cell scrambler multiplies input data by X
43
and then divides the result by X
43
+1. Thus, the cell scrambler outputs a 48-byte scrambled result.
FIG. 6
shows the structure of the cell descrambling circuit
2
. A descrambled ATM cell sequence
101
is sent to a 43-staged shift register
21
. When a disable signal
103
is inactive, the 43-staged shift register
21
shifts the scrambled ATM cell sequence
101
. When the disable signal
103
is active, the 43-staged shift register
21
does not shift the scrambled ATM cell sequence
101
. The 43-staged shift register
21
delays the scrambled ATM cell sequence
101
in 43 stages. When the disable signal
103
is inactive, an adding circuit
22
outputs the added results of the delayed data in 43-staged shift register
21
and the scrambled ATM cell sequence
101
. When the disable signal
103
is active, the adding circuit
22
outputs the scrambled ATM cell sequence.
FIG. 7
shows the relation between a scrambled ATM cell sequence and a descrambling operation performed by a conventional descrambling circuit. Referring to
FIG. 7
, each ATM cell is composed of a header portion (5 bytes) and a payload portion (48 bytes). Thus, the length of each ATM cell is 53 bytes. The ATM cell sequence contains necessary ATM cells that are used in a higher layer and unnecessary ATM cells such as idle cells (blank cells) and unassigned cells. The cell descrambling circuit descrambles only the payload portion (other than the header portions) of each ATM cell of the scrambled ATM cell sequence regardless of whether the ATM cell is necessary or unnecessary. The cell descrambling circuit outputs the descrambled ATM cell sequence by descrambling the cell scrambled ATM cell sequence.
The conventional ATM cell descrambling circuit descrambles all scrambled ATM cells. Thus, the conventional ATM cell descrambling circuit descrambles unnecessary ATM cells that are not used in a higher layer (such as idle cells and unassigned cells). Consequently, since the descrambling operation is performed for unnecessary ATM cells, the power consumption of the circuit is increased.
SUMMARY OF THE INVENTION
The present invention made from the above-described point of view. An object of the present invention is to provide a cell descrambling circuit that stops a cell descrambling operation for unnecessary ATM cells such as idle cells and unassigned cells that are not used in a higher layer for a predetermined period so that necessary ATM cells are normally descrambled and thereby the power consumption of the circuit is decreased.
A first aspect of the present invention is an ATM cell descrambling circuit for detecting a header portion and a payload portion of each cell of a scrambled ATM cell sequence in the state that each cell pre- or fully-synchronizes, descrambling the payload portion, and outputting a descrambled ATM cell sequence, the circuit comprising a means for -determining whether each ATM cell is an unnecessary ATM cell that is not used in a higher layer of an ATM communication so as to stop a cell descrambling operation for a predetermined period.
The predetermined period is a period just after the header portion of an unnecessary ATM cell until the beginning of data necessary for the normal ATM cell descrambling operation for the next ATM cell.
When unnecessary ATM cells successively take place, the predetermined period is a period just after the header portion of the first unnecessary ATM cell until the beginning of data necessary for the normal ATM cell descrambling operation for a necessary ATM cell just preceded by the last unnecessary ATM cell.
A second aspect of the present invention is an ATM cell descrambling circuit for detecting a header portion and a payload portion of each cell of a scrambled ATM cell sequence in the state that each cell pre- or fully-synchronizes, descrambling the payload portion, and outputting a descrambled ATM cell sequence, the circuit comprising a cell header pattern extracting means for inputting the scrambled ATM cell sequence and a cell header signal, a unnecessary cell detecting means for inputting a cell header pattern extracted by the cell header pattern extracting means and outputting an unnecessary cell detection signal, an unnecessary cell timing assigning means for inputting the cell header signal and the scrambled ATM cell sequence and outputting a cell descrambler disable signal and a cell scrambler input data corresponding to the unnecessary cell detection signal, and a cell descrambler circuit for descrambling the cell descrambler input data corresponding to the cell descrambler disable signal.
According to the present invention, unnecessary ATM cells such as idle cells and unassigned cells that are not used in a higher layer are detected. A cell descrambling operation is stopped for such unnecessary ATM cells. Thus, since the cell descrambling operation is performed for only necessary cells, the power consumption of the circuit can be decreased.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5161193 (1992-11-01), Lampson et al.
patent: 5444782 (1995-08-01), Adams, Jr. et al.
patent: 5594869 (1997-01-01), Hawe et al.
patent: 5642421 (1997-06-01), Gray et al.
patent: 0 714 186 (1996-05-01), None
patent: 0 717 411 (1996-06-01), None
patent: 5-95366 (1993-04-01), None
patent: 9-83391 (1997-03-01), None
“Self-synchronizing Scambler”, ANSI T1. 646-1995 11.3, pp. 26-27.
Japanese Office Action dated Mar. 4, 1999, with partial translation.
German Office Action dated Oct. 27, 1999, with English translation.
McGinn & Gibb PLLC
Peeso Thomas R.
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