Asynchronous signal input apparatus and sampling frequency...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C710S053000, C710S056000, C710S061000, C710S310000, C365S189050, C365S230080

Reexamination Certificate

active

07450678

ABSTRACT:
In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.

REFERENCES:
patent: 6118344 (2000-09-01), Toshitani et al.
patent: 6263036 (2001-07-01), Yamamoto
patent: 11-55075 (1999-02-01), None

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