Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-05-20
2001-11-27
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
06324235
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention generally relates to circuits for converting input data received at a first sample rate into corresponding output data at a second sample rate. More particularly, this invention relates to tracking an input sample rate to maintain a relationship between the rate at which input data is received and the rate at which output data is provided.
Many audio devices, such as computer sound cards and recording studio equipment, receive, transmit, and manipulate audio information in a digital, rather than analog, form. Some audio sources, such as compact-disk players, Z-Video players, and digital video disks, generate a digital signal directly. Other audio sources, such as microphones, generate an analog signal, which can be converted to a digital signal with an analog-to-digital converter (“ADC”). An ADC typically “samples” the analog signal at a rate high enough to preserve the acoustic characteristics of the analog audio signal. However, with either data from a digital signal source, or from an analog signal source converted by an ADC, the data rate of the source may be different from the rate at which a digital audio device manipulates data. Digital audio devices that can receive digital data streams from a variety of sources at a variety of data rates often include digital sample rate converters that convert the input sample rate to an output sample rate that is compatible with the digital audio device.
Digital sample rate converters can be either synchronous or asynchronous. A synchronous sample rate converter shares a common time base, or clock, with the input signal source. In order for a synchronous sample rate converter to operate, it must be able to lock to the clock signal used by the input device, and the input device must provide a clock output or a third device must provide a common clock output. An asynchronous sample rate converter does not require a common time base with the input signal source, and can accept input data from a wide variety of sources. An asynchronous digital sample rate converter can convert between any two sample rates within the operating range of the converter.
One type of asynchronous digital sample rate converter takes an input sample stream, converts it to an analog signal with a digital-to-analog converter (DAC), and then converts that analog signal back to a digital signal at the desired output sample rate with an ADC. This approach is simple to understand and direct, but is complex to implement and produces an inferior signal because of the distortion and noise that the ADC and DAC add.
An alternative to asynchronous digital sample rate conversion is to use a phase-locked-loop approach. The phase-locked loop approach adapts the output data rate to the input data rate by adjusting the internal clock rate of the receiving device to the clock rate of the input device. The clock rate of the input device and the internal clock rate are both provided to a mixer, the mixer output, or product, is zero when the two rates are the same, and when the two clock rates are not the same, the mixer output is converted into a signal that adjusts the internal clock rate. This process can take several seconds to achieve lock and limits input data to those signals with a clock rate within the tuning range of the internal clock. The time-to-lock can be especially undesirable if the input clock rate is not constant, but drifts or otherwise changes. Another disadvantage of this approach is that, while the two clock rates are frequency matched, no phase relationship between the input and output data is maintained, which could lead to a loss of input data if the input data overwrites valid data. This also precludes the use of more than one asynchronous stream at a time, or mixing of a fixed-rate internal signal with the external asynchronous signal.
Many sample rate converters temporarily store the input data in a random-access memory (“RAM”), or other type of memory, to buffer the data while the sample rate conversion process proceeds. The RAM has a finite capacity and can not store an endless stream of input data; therefore, once an input value is read from a RAM address, that address becomes available for another input data point.
FIG. 1
shows a simplified representation of a buffer
10
that is configured as a circle for illustrative purposes. Each segment
3
of the buffer represents an address where a data point may be written to or read from. The next input data point will be read into the buffer at the input data pointer location
5
, writing over the value stored in that location, which has already been read. The next output data point will be read from the buffer at the output data pointer location
7
. Both pointers will increment in the same direction around the buffer, represented by arrows, according to the input sample rate
9
and the output sample rate
11
. The distance between the input pointer
5
and the output pointer
7
is represented as a phase angle
8
. If the input sample rate suddenly increases, the input data pointer might overrun the output data pointer, writing over data that has not yet been read. In a phase-locked system that does not account for the phase relationship between the input data sample rate and the output data sample rate, small excursions in the input data sample rate might cause the input data pointer to overrun valid data in the buffer.
Therefore an asynchronous sample rate tracker that achieves lock quickly and maintains an optimum input buffer configuration and signal fidelity is desirable.
SUMMARY OF THE INVENTION
According to the present invention, a method and apparatus of tracking and locking to an asynchronous input sample rate is provided for use in a digital device, for example a digital audio sound card. In an embodiment, a read rate is estimated according to the slope of the phase error between an input sample rate and a read rate, and phase correction is provided according to the read rate and the phase error. A convolver converts the read rate to an output rate at the internal data rate of the digital device.
In a specific embodiment, a phase detector produces a phase error signal based on the positions of a write pointer and a read pointer in a FIFO buffer. The FIFO buffer receives data at an input data rate that is asynchronous to the internal data rate of the digital device receiving the input data. A differentiator in a phase estimator produces a phase error slope signal that is provided to a scaler that adjusts the read rate based on the current read rate correction step size and the magnitude of the phase error slope. The scaler is a binary shift register, but could be a multiplier.
In another embodiment, a step size adjuster adjusts the read rate correction step size according to the sign of the phase error slope. The step size is increased if the sign of the slope remains the same for a selected number of cycles, and is decreased if the sign of the slope changes or is zero for selected numbers of cycles. The step size adjustment is applied to a current step size, which may be used by the scaler in adjusting the read rate.
In yet another embodiment, a phase corrector produces a phase correction signal to momentarily alter the read rate to restore a selected phase relationship between the read pointer and the write pointer. The phase correction signal is generated from the phase error signal and the read rate to rapidly restore the desired phase without unduly affecting the output of the rate converter.
REFERENCES:
patent: 4388727 (1983-06-01), Metcalf
patent: 4941156 (1990-07-01), Stern et al.
patent: 5230097 (1993-07-01), Currie et al.
Rossum David
Savell Thomas C.
Backus , Jr. Kenneth R.
Burd Kevin M
Creative Technology Ltd.
Pham Chi
Townsend and Townsend / and Crew LLP
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