Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2011-06-28
2011-06-28
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C326S093000
Reexamination Certificate
active
07971038
ABSTRACT:
An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).
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Chan Eddie P
NXP B.V.
Vicary Keith
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