Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-01-09
2004-01-27
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S206000, C365S207000, C365S208000
Reexamination Certificate
active
06683818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory and, more particularly, to clocking an asynchronous random access memory (“RAM”) to minimize power consumption. Clocking an asynchronous RAM achieves the speed and flexibility of conventional asynchronous RAM cells, but with reduced power of synchronous RAM cells.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
High-speed Random Access Memory devices, or RAM, employ either synchronous or asynchronous control signals, each of which have advantages and disadvantages. Asynchronous RAM apply power to the sense amplifiers during the entire read cycle -during both the access and sense portion of the read cycle. This causes excessive current draw while allowing the address access time to be met at any time during the cycle. Synchronous RAM solves the current problem, but at the expense of a very short access window. Specifically, the full address access time must be met during the rising edge of the synchronizing control clock.
Disadvantages of asynchronous technology are readily apparent in any design where reducing power consumption is necessary. Powering the sense amp during the entire read cycle causes the high current sense amp to be active for a long period. Another disadvantage of using an asynchronous RAM is the need to create a precise write strobe. In order for a series of writes to take place on single-clock-per-write bursts, a write strobe must be created that is less than a single clock period wide. This is normally done by adding some amount of logic to gate the clock with a write control. This logic must then be carefully synthesized, routed, and verified at every stage of the design.
The second alternative is to use a synchronous RAM. That, too, is difficult in most synthesized logic integrated circuits where there is a moderate amount of combinatorial logic both in the address path prior to the RAM cell (“macro”) and in the data path after the RAM macro. The synchronous clock would have to be precisely aligned to occur at a time after the address has arrived at the RAM and been decoded, but early enough in order to allow the sense amp to access the data and have that data flow through the logic after the RAM prior to the next bank of flip-flops. Although it is theoretically possible to make the alignment, it is exceedingly difficult to match the alignment of the clock rising edge with the arrival of the address. The address delay will carry as it flows through many levels of logic, and is influenced by a combination of gate delays and routing delays, such that the precise nature of these delays varies considerably over a wide range of fabrication processes. With the routing delay accounting for more than half of the delay, it is not possible to ensure that the delays within the RAM to align the clock will track the address delays across the full process range of fast/slow transistors, high/low sheet resistance, large/small capacitance and variances thereof.
Therefore, it may be desirable to combine the benefits of an asynchronous RAM with the benefits of a synchronous RAM to create a “hybrid” async/sync RAM in the form of a clock enhanced asynchronous RAM. The desired RAM may function during a subset of a full clock period to reduce power consumption, while allowing relaxed setup time requirements to read or write data.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an asynchronous RAM that allows RAM internal logic to precisely gate the clock during write cycles as well as read cycles. The clock is used to enable a write transaction during the second half of the write cycle (when the clock is low). For reads, the clock is used to enable the sense amplifiers only during the second half of the cycle (also when the clock is low). A separate write-enable (WE) signal is used in order to distinguish between read and write during the first half of the cycle (when the clock is high). A standard chip select is used to enable the function of the RAM. Optionally, a latch is added to the output stage of the RAM to capture the data during the read cycle in cases where additional hold time (beyond the end of the clock low period) is desired.
The address decoding occurs during the first half of the clock cycle and the sense amplifiers are enabled during the second half. The flexibility of the read access is such that the address can arrive before the mid-point of the read cycle, at which point the sense amplifiers allow the read data to flow through quickly leaving more than a third of the cycle for post-RAM combinatorial delays. In cases where the majority of the delay is prior to the RAM, the sense amplifiers remain active during the second half so that the address can arrive towards the end of the cycle and the correct data is still read out of the RAM. It can be seen, therefore, that nearly the full range of flexibility of a fully asynchronous RAM macro is preserved.
However, the current/power requirements are reduced by half, since the sense amplifiers are not enabled during the first half of the cycle. For writes, the write enable is active the entire cycle so that the sense amplifiers are never activated. This is an improvement over conventional asynchronous RAM macros in which a “false” read is started at the beginning of the cycle (during the period when the combinatorial logic is creating and setting up the write address lines) before the write strobe can be activated indicating a write cycle. By avoiding a “false” read during the first half of the write, the current requirement during the write is reduced by more than 50% (since the sense amplifiers operating during the first half of the write overwhelmed the actual current needs of a write).
Thus, the present invention includes an asynchronous memory circuit including one or more sense amplifiers and a clock circuit, which may be configured to generate a clock signal. For example, the clock signal may be generated by a counter followed by a flip-flop. Alternatively, the clock signal may be generated by any other circuit element, or combination of circuit elements, capable of generating a cyclical signal. The one or more sense amplifiers may be configured to operate in response to the clock signal and a control signal, such that the control signal may indicate the occurrence of either a read or write cycle. The asynchronous memory circuit may further include a combinatorial logic circuit, which may combine the clock signal and control signal to produce a read enable signal. In addition, the one or more sense amplifiers may receive the read enable signal from the combinatorial logic circuit, such that the read enable signal may activate the one or more sense amplifiers only during a portion of a read cycle.
The present invention also includes a method for reducing the power consumption in an asynchronous memory circuit. Such a method may include activating one or more sense amplifiers only during a second half of a read cycle, and deactivating one or more sense amplifiers during an entire write cycle. In this manner, the method may disable the sense amplifiers for substantially half the amount of time needed in conventional asynchronous memory circuits.
Furthermore, the present invention may include a sense amplifier configured to detect a voltage difference on a bit line of a memory array only during a select portion of a clock signal. The sense amplifier may include at least one transistor coupled between a differential amplifier and a power supply or ground connection. The transistor may be adapted to receive a read enable signal, such that the read enable signal may activate the sense amplifier only during the select portion of the clock signal.
REFERENCES:
patent: 5422858 (1995-06-01), Mizukami et al.
patent: 5563835 (1996-10-01), Oldham
patent: 5881007 (1999-03-01), Jeong et al.
patent: 5940334 (1999-08-01), Holst
patent: 6249482 (2001-06-01), Albon et al.
Berzins Mathew S.
Cornell Charles A.
Larky Steven P.
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Dinh Son T.
LandOfFree
Asynchronous random access memory with power optimizing clock does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous random access memory with power optimizing clock, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous random access memory with power optimizing clock will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3227715