Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2005-10-25
2005-10-25
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S094000, C326S095000
Reexamination Certificate
active
06958627
ABSTRACT:
An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized. The asynchronous pipeline may incorporate logic elements to combine data, as well as matched delay elements for the request, acknowledgment, and done signals. The asynchronous pipeline may also incorporate clocked CMOS logic gates. Fork and join structures are also provided by the asynchronous pipeline design.
REFERENCES:
patent: 6028453 (2000-02-01), Kong
patent: 2002/0069347 (2002-06-01), Singh
patent: 0913768 (1999-05-01), None
patent: 0182053 (2001-11-01), None
patent: 0182064 (2001-11-01), None
patent: 0195089 (2001-12-01), None
McLaughlin K et al: “A static technique for high-speed CMOS state machine design” ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International Rochester, NY USA Sep. 19-23, 1994, New York, NY, USA IEEE, (Sep. 19, 1994), pp. 108-111, XP010140513 ISBN: 0-7803-2020-4 the whole document.
M. Borah, R.M.Owens, and M.J. Irwai, High-throughput low-power DSP using clocked CMOS circuitry. InProc. In Symp. on Low-Power Design,pp. 139-144, 1995.
A. Davis and S.M.Nowick, Asynchronous circuit design: Motivation, background, and methods. In G.Birswistle and A. Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pp. 1-49. Springer-Verlag, 1995.
P. Day and J.V. Woods, Investigation into micropipeline latch design styles. IEEE TVLSI 3(2):264-272, Jun. 1995.
A. Doopley and K. Yun. Optimal clocking and enhanced testability for high-performance self-resetting domino properties, inConference on Advanced Research in VLSI,1999.
H. v. Gagledonk, D. Baumann, K. van Berkel, D. Gloor, A. Peeters, and G. Stegmann. An asynchronous low-power 80C51 microcontroller. InProc. Intl. Symp. Adv. Res. Async. Circ. Stst.(ASYNC), pp. 96-107,1998.
D. Harris and M. Horowitz. Skew-tolerant domino circuits.IEEE JSSC.32(11):1702-1711, Nov. 1997.
Q. Hauck, M. Garg, and S.A.Huss, Two-phase asynchronous wave-pipelines and their application to a 2D-DCT. InProc. Intl. Symp. Adv. Res. Async. Circ. Stst.(ASYNC), Apr. 1999.
W. Liu, C.T. Gray, D. Fan, W.J. Farlow, T.A. Hughes, and R.K. Cavin. A 250-MHz wave pipelined adder in 2-μm CMOS.IEEE JSSC, 29(9):1117-1128, Sep. 1994.
C. Molnar, I. Jones, W. Coates, J. Lexau, S. Fairbanks, and I. Sutherland. Two FIFO ring performance experiments. Proceedings of theIEEE, 87(2):297-307, Feb. 1999.
A. Mukherjee, R. Sudhakar, M. Marke-Sadowska, and S. Long. Wave steering in YADDs: a novel non-iterative syntheses and layout technique. InProc. DAC.1999.
V. Narayanan, B. Chappell, and B. Fleischer. Static timing analysis for self resetting circuits. InProc. ICCAD,1996.
S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins, Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. InProc. ISSCC,Feb. 2000.
C.L. Seitz, “System Timing”, Introduction to VLSI Systems, Ch. 7, Addison-Wesley, 1980.
M. Singh and S. M. Nowick, Fine-grained pipelined asynchronous adders for high-speed DSP applications. InIEEE Computer Society Annual Workshop on VLSI,IEEE Computer Society Press, Apr. 2000.
M. Singh and S. Nowick. High-throughput asynchronous pipelines for fine-grain dynamic datapaths. InProc. Ind. Symp. Adv. Res. Async. Circ. Syst.(ASYNC), 2000.
I.E. Sutherland, Micropipelines,Communications of the ACM,32(6):720-738, Jun. 1989.
C. van Berkel. M. Josephs, and S. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223-233, Feb. 1999.
T. Williams. Self-Timed Rings and their Application to Division, Ph.D. thesis, Stanford University, Jun. 1991.
D. Wong, G. De Micheli, and M. Flynn. Designing high-performance digital circuits using wave-pipelining. IEEE TCAD, 12(1):24-46, Jan. 1993.
G. Yee and C. Sechen, Clock-delayed domino for adder and combinational logic design. InProc. ICCD,Oct. 1996.
K.Yun, P. Beerel, and J. Arceo. High-performance asynchronous pipeline circuits. InProc. Intl. Symp. Adv. Res. Async. Circ. Syst.(ASYNC), 1996.
J. Ebergen, “Squaring the FIFO in GasP,”Proc. Intl. Symp. Adv. Res. Async. Circ. Syst.(ASYNC), pp. 194-205, IEEE Computer Society Press, Mar. 2001.
S.B. Furber and P.Day, “Four-Phase Micropipeline Latch Control Circuits,”IEEE TVLSI,4(2):247-253, Jun. 1996.
S.M.Nowick et al., Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders,Proc. Intl. Symp. Adv. Res. Async. Circ. Syst.,IEEE Computer Society Press, Apr. 1997, pp. 210-223.
I. Sutherland and S. Fairbanks, “GasP: A Minimal FIFO Control,”Proc. Intl. Symp. Adv. Res. Async. Circ. Syst.(ASYNC), pp. 46-53, IEEE Computer Society Press, Mar. 2001.
International Application Ser. No. PCT/US01/29721, International Search Report, Sep. 21, 2001.
Montek Singh and Steven M. Nowick, MOUSETRAP: Ultra High-Speed Transition-Signaling Asynchronous Pipelines, ACM “Tau-00” workshop (Dec. 4-5, 2000), ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. (This is the same as Provisional Appl. No. 60/242,587.).
S. Furber, “Computing without Clocks: Micropipelining the ARM Processor,”Asynchronous Digital Circuit Design, Workshops in Computing(eds. G. Birtwistle et al.), Springer-Verlag, 1995, pp. 211-262 No month.
Nowick Steven M.
Singh Montek
Tran Anh Q.
Trustees of Columbia University in the City of New York
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