Asynchronous pipeline whose stages generate output request befor

Details Asynchronous pipeline whose stages generate output request befor Asynchronous pipeline whose stages generate output request befor

1997-09-02

1999-07-06

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

3649262, G06F 1200

Patent

active

059208996

ABSTRACT:
An asynchronous pipeline that is divided into separate data and signal chains by moving the data register load signal buffer outside of the closed loop that generates the output request event from the input request event, causing the output request event to occur before output data is available. Matched delays between adjacent pipeline stages permit data and signals to move from stage to stage without problem. Matched delays between stages are possible if: (1) every stage has the same loading; (2) logically adjacent stages are physically located next to each other; (3) the buffered data register load signal has enough drive to latch data reliably; and (4) the delay from input request event to output request event is greater than the latch time of the data register. Input and output circuits transform the internal signals of the pipeline to the correct asynchronous signals for asynchronous source and destination devices or to the correct synchronous signals for synchronous source and destination devices.

REFERENCES:
patent: 4819201 (1989-04-01), Thomas et al.
patent: 5550780 (1996-08-01), Chu
patent: 5663994 (1997-09-01), Chu
Kenneth Y. Yun et al., High-Performance Asynchronous Pipeline Circuits (Mar. 1996).

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