Asynchronous non-blocking snoop invalidation

Details Asynchronous non-blocking snoop invalidation Asynchronous non-blocking snoop invalidation

2005-09-13

2005-09-13

Vital, Pierre (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S141000

Reexamination Certificate

active

06944721

ABSTRACT:
A method and system for avoiding live locks caused by repeated retry responses sent from a first cache memory that is in the process of manipulating a cache line that a second cache memory is attempting invalidate in the first cache memory. To a live lock condition caused by multiple caches subsequently manipulating the cache line, thus resulting in multiple retry responses back to the second cache memory, a “kill bit” is set in a snoop and read/claim (RC) queue associated with the first cache memory. The kill bit instructs the first cache memory to acknowledge the kill command from the second cache memory, but allows the first cache memory to complete the current manipulation of the cache line, after which the first cache memory kills the cache line.

REFERENCES:
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5996049 (1999-11-01), Arimilli et al.
patent: 6336169 (2002-01-01), Arimilli et al.
patent: 6347361 (2002-02-01), Arimilli et al.
patent: 6405289 (2002-06-01), Arimilli et al.

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