Asynchronous, multi-rail digital circuit with gating and...

Details Asynchronous, multi-rail digital circuit with gating and... Asynchronous, multi-rail digital circuit with gating and...

2007-07-31

2009-10-13

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C327S385000

Reexamination Certificate

active

07603635

ABSTRACT:
A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.

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Vivek Tiwari et al. “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design” IEEE Transactions on Computer-Aided Design Journal (TCAD), 1996, 21 pages.
J. Cortadella et al. “Coping with the Variability of Combination Logic Delays” Proceedings of the International Conference on Circuit Design (ICCD), Oct. 2004, 6 pages.

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