Asynchronous-mode sync FIFO having automatic lookahead and...

Details Asynchronous-mode sync FIFO having automatic lookahead and... Asynchronous-mode sync FIFO having automatic lookahead and...

2007-10-23

2007-10-23

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S061000, C713S400000, C375S354000, C365S189011, C365S189080

Reexamination Certificate

active

11033561

ABSTRACT:
Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.

REFERENCES:
patent: 2002/0087909 (2002-07-01), Hummel et al.
“AMD-3181™ HyperTransport™ PCI-X® Tunnel Data Sheet”, 24637 Rev. 3.02, Aug. 10, 2004, pp. 1-87.

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