Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-09-27
2011-10-11
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S163000, C711S154000, C711S159000, C711SE12075
Reexamination Certificate
active
08037249
ABSTRACT:
A method for queuing asynchronous memory accesses includes pinning memory buffers in a managed memory environment, issuing data transfer requests to a peripheral device, each request corresponding to at least one of the pinned memory buffers, and asynchronously accessing at least one of the pinned buffers responsive to the requests.
REFERENCES:
patent: 2004/0168035 (2004-08-01), Romanufa et al.
patent: 2005/0289549 (2005-12-01), Cierniak et al.
patent: 2009/0037936 (2009-02-01), Serebrin
Bragdon Reginald
Cardwell Eric S
Cypress Semiconductor Corporation
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