Asynchronous logic circuit for 2-phase operation

Details Asynchronous logic circuit for 2-phase operation Asynchronous logic circuit for 2-phase operation

1994-11-02

1995-12-26

Westin, Edward P.

Electronic digital logic circuitry

Accelerating switching

326 98, 326121, 326119, H03K 1901, H03K 190948

Patent

active

054791073

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to an asynchronous logic circuit.
A logic circuit of the generic type is presented, for example, in the Patent Application submitted to the German Patent Office with the official designation P 41 15 081.3 corresponding to U.S. Ser. No. 08/146,061 and constitutes a prior art in terms of PatG .sctn.3 (2)/EPC Art. 54 (3). This is a logic circuit in which a plurality of input lines is connected both to a logic block made of n-channel field-effect transistors and to a logic block which is inverse with respect thereto and consists of p-channel transistors (split transistor switch logic), in which both blocks are connected both to a precharging transistor and a charging transistor in each case and in which the transistors which are connected to the first block can be driven directly and the transistors which are connected to the other logic block can be driven indirectly via an inverter by means of an request signal, precharging taking place in a first state (low) of the request signal and charging or evaluation taking place in the second state (high) in accordance with the logic connection prescribed by the logic blocks.
The European Patent Application with the Publication Number 0 147 598 discloses a clocked differential cascade voltage switching logic system (CVS logic system) in which a first switching device and a second switching device are provided whose first outputs are connected in each case via transistors to the supply voltage and whose second outputs are connected in each case via transistors to reference potential, the second switching device being supplied with input signals which are complementary to the input signals of the first switching device and the second switching device switching through precisely when the first switching device does not switch through, and vice versa.


SUMMARY OF THE INVENTION

The invention is based on the object of disclosing an asynchronous logic circuit which can be operated in 2-phase mode (signal edge-controlled) and not as is otherwise customary in 4-phase mode (status-controlled) and which requires the smallest possible degree of outlay in terms of circuitry.
This object is achieved according to the invention by an asynchronous logic circuit having first and second logic blocks. A first output of the first logic block is connected via a first field-effect transistor of a first conduction type to a supply voltage terminal and a second output of the first logic block is connected via a first field-effect transistor of a second conduction type to a reference potential terminal.
A first output of the second logic block is connected via a first field-effect transistor of a first conduction type to a supply voltage terminal and a second output of the second logic block is connected via a first field-effect transistor of a second conduction type to a reference potential terminal.
The first logic block contains only field-effect transistors of the first conduction type and the second logic block contains only field-effect transistors of the second conduction type. Both logic blocks are connected to the same input lines.
The first and second logic blocks have switching behaviors which are complementary to one another. The first output of the first logic block is switched through, as a function of control signals of the input lines, to the second output of the first logic block precisely when the first output of the second logic block is not switched through to the second output of the second logic block, and vice versa.
The respective gate of the first field-effect transistor of the first conduction type, of the first field-effect transistor of the second conduction type, of the second field-effect transistor of the first conduction type and of the second field-effect transistor of the second conduction type is connected to a request input.
A ready-message output is connected via third and fourth field-effect transistors of the first conduction type to the supply voltage terminal. The gate of the third field-effect trans

REFERENCES:
patent: 5117133 (1992-05-01), Luebs
patent: 5371424 (1994-12-01), Quigley et al.
patent: 5382844 (1995-01-01), Knauer
Electronics Letters, vol. 25, No. 3, "Evaluation of Self-Timed Systems for VLSI", Patel et al, 2 Feb. 1989, pp. 215-217.
Electronics Letters, vol. 23, No. 6, "Self: A Self-Timed Systems Design Technique", Stevenage, 12 Mar. 1987, pp. 269-270.

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