Asynchronous jitter reduction technique

Details Asynchronous jitter reduction technique Asynchronous jitter reduction technique

2004-02-10

2009-02-24

Portka, Gary J (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C365S233170, C710S061000

Reexamination Certificate

active

07496728

ABSTRACT:
The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency xfnwhere x is a whole integer and fnis the frequency at which the memory is clocked to write data. Read Addresses are applied to the FIFO at a frequency on the order of fnto identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations. The duration of at least one successive Read Addresses is altered in response to memory usage status to maintain memory capacity below a prescribed threshold.

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