Asynchronous input/output for integrated circuits that latches e

Details Asynchronous input/output for integrated circuits that latches e Asynchronous input/output for integrated circuits that latches e

1997-12-17

2000-03-21

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

326 46, 326 93, 327155, G06F 1314

Patent

active

060413719

ABSTRACT:
An asynchronous latch including a finite state machine (301) and a level-sensitive latch (304) in a feedback path of the finite state machine. The input to the level-sensitive latch (304) is a signal generated by decoding the state of the finite state machine (301). The level-sensitive latch output is fed back to the finite state machine inputs to control next-state transitions. An asynchronous input line couples an asynchronous signal to the level-sensitive latch so that the asynchronous signal is used as a latching signal.

REFERENCES:
patent: 4939394 (1990-07-01), Hashimoto
patent: 5389838 (1995-02-01), Orengo
patent: 5555213 (1996-09-01), DeLong
patent: 5834957 (1998-11-01), Staton
Yun, K.Y.; Dill, D.L., "Unifying synchronous/asynchronous state machine synthesis," Computer-Aided Design, 1993. Digest of Technical Papers, 1993 IEEE/ACM International Conference, pp. 255-260.

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