Asynchronous input/output cache having reduced latency

Details Asynchronous input/output cache having reduced latency Asynchronous input/output cache having reduced latency

2006-04-25

2006-04-25

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S145000, C711S141000, C711S147000, C711S167000, C711S130000, C711S162000, C709S241000, C713S400000, C713S502000, C713S600000, C710S019000, C710S027000, C710S055000, C710S061000, C710S107000, C710S125000, C710S200000, C710S240000, C710S244000, C710S305000

Reexamination Certificate

active

07035981

ABSTRACT:
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus. In accordance with another aspect of the present invention, a method is provided for buffering or caching data in a shared relationship between a system data bus and an input/output (I/O) data bus, which includes the steps of providing a single data storage area in communication with both a system data bus and an I/O data bus, and providing a single address storage area configured to store system memory addresses corresponding to data contemporaneously stored in the data storage area. In accordance with the broad aspect of the invention, the method further replicates a portion of validation circuitry in both a system frequency domain and an I/O frequency domain. In this way, latency delays encountered when crossing a frequency domain boundary are encountered at times outside a critical path.

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