Asynchronous, independent and multiple process shared memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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Details

C711S154000, C711S149000, C711S218000, C710S052000, C365S221000

Reexamination Certificate

active

10644621

ABSTRACT:
The present invention provides a system and method for implementation and use of a shared memory. The shared memory may be accessed both independently and asynchronously by one or more processes at corresponding nodes, allowing data to be streamed to multiple processes and nodes without regard to synchronization of the plurality of processes. The various nodes may be adaptive computing nodes, kernel or controller nodes, or one or more host processor nodes. The present invention maintains memory integrity, not allowing memory overruns, underruns, or deadlocks. The present invention also provides for “push back” after a memory read, for applications in which it is desirable to “unread” some elements previously read from the memory.

REFERENCES:
patent: 6134629 (2000-10-01), L'Ecuyer
patent: 6807590 (2004-10-01), Carlson et al.
patent: 2003/0131162 (2003-07-01), Secatch et al.

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